ASIC Design Verification Engineer, Platforms and Devices

Google LLC

Mountain View, CA

JOB DETAILS
SALARY
$138,000–$198,000 Per Year
SKILLS
ASIC Design, ASIC Verification, Analysis Skills, Architectural Services, Building Systems, Computer Architecture, Computer Engineering, Computer Science, Debugging Skills, Design Verification, Develop Methodologies, Electrical Engineering, English Language, Equal Employment Opportunity (EEO), FPGA, Functional Testing, Genetics, Hardware Architecture Design, IP (Internet Protocol), Intrusion Prevention Systems, Leading Edge Technology, Memory Hardware, Memory Management, Memory Subsystem, Microprocessor, PCI Express (PCI-E), Problem Solving Skills, Prototyping, Recruiting/Staffing Agency, Regulatory Requirements, Research & Development (R&D), Scripting (Scripting Languages), Simulation, Software Development, System Test, SystemVerilog, Team Player, Technical/Engineering Design, Test Design, Testing, Topology, Verification Engineering
LOCATION
Mountain View, CA
POSTED
30+ days ago

ASIC Design Verification Engineer Platforms and Devices - Google Careers

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Job Title: ASIC Design Verification Engineer Platforms and Devices

Location: Mountain View, CA, USA

Job Type: Full-time

About the Job:

Be part of a team that pushes boundaries developing custom silicon solutions that power the future of Googles direct-to-consumer products. Youll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences delivering unparalleled performance efficiency and integration.

About the Role:

As a part of the Google Silicon Platforms team, you will work on the verification of the backbone of Googles SOC offerings. You collaborate with hardware architects and design engineers for functional and performance verification of the infrastructure IP interconnects, caches, memory management, and system services. You will also work on developing high-performance VIPs for protocols supported by our SOCs and closely collaborate in the deployment of the verification stack across a heterogeneous set of IPs. Our approach to building systems is based on scalability. Your work will include building and verifying a generalized class of system topology abstractions and developing the associated methodologies and tools needed to solve the problem. As an ASIC Design Verification Engineer, you will be part of a Research and Development team and your responsibilities will include building verification components, constrained-random testing, system testing, and verification closure.

Responsibilities:

  • Plan and execute the verification of the next generation configurable Infrastructure IPs interconnects and memory subsystems.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct blocks and subsystems.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.

Requirements:

  • Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience verifying digital logic at RTL level using SystemVerilog or CC.
  • Experience creating and using verification components and environments in standard verification methodology (e.g., UVM, SVA, CRV, PSS, or LPDV).
  • Experience verifying digital systems using standard IP components (e.g., interconnects, e.g., microprocessor cores, hierarchical memory subsystems).
  • Experience with scripting languages and SW development frameworks.
  • Preferred qualifications:
  • Masters degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
  • 7 years of experience with building verification methodologies that span simulation, formal emulation, and FPGA prototyping.
  • Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
  • Experience with performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation.
  • Architectural background in one or more of Caches, Hierarchies, Coherency, Memory Consistency Models, DDR, LPDDR, PCIe, Packet Processors, Security, Clock, and Power Controllers.

What We Offer:

  • Competitive salary range: $138,000 - $198,000 per year.
  • Bonus, equity, and benefits.
  • Opportunity to work on cutting-edge technology and contribute to the innovation behind Googles products.
  • Collaborative and dynamic work environment.
  • Professional development opportunities.

How to Apply:

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies, Google does not accept agency resumes. Please do not forward resumes to our jobs alias Google employees or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

About Google:

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity, expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition, including breastfeeding, expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Googles EEO Policy, Know your rights, workplace discrimination is illegal, Belonging at Google, and How we hire.

Equal Opportunity:

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity, expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition, including breastfeeding, expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Googles EEO Policy, Know your rights, workplace discrimination is illegal, Belonging at Google, and How we hire.

About the Company

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Google LLC