ASIC Engineer, Foundry and IP

Meta is building custom silicon to power the next generation of AI infrastructure and immersive computing experiences. The Infrastructure Silicon team is responsible for designing and delivering high-performance, power-efficient ASICs that underpin Meta's data center and AI workloads. We are looking for individuals with experience in foundry technology benchmarking and PPA analysis, stdcell circuit design and characterization, memory compiler PPA optimization and test chip design and testing. Analyze and benchmark foundry process offering with physical design teams to identify optimal technologies for product roadmaps Drive early PPA evaluation of foundation IP drops by running preliminary PnR experiments to identify issues and opportunities for improvement Architect, design, and characterize high-performance, low-power, and ultra-high-density standard cell libraries with foundry partners and Physical design teams Run transistor-level simulations (SPICE), direct custom physical layouts, and manage automated library characterization flows Evaluate, benchmark, and choose third-party memory compilers (SRAM, Register Files, ROM) based on rigorous PPA and trade-off metrics Participate in physical implementation, and tape-out of silicon test chips targeted at proving out new foundation IP, custom structuresBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience in a foundry team driving PPA analysis and engineering army benchmarking Deep understanding of CMOS device physics, digital circuit design, and advanced node layout constraints Proven track record of participating in test chip tapeouts. Hands-on experience in owning end to end design and sign-off of partitions on a test chip Expert-level command of design environments like Cadence Virtuoso, HSPICE, Spectre Working knowledge of synthesis, PnR, STA and PDV tools to converge a block on a test chip High proficiency in scripting with Python, TCL, Perl, or SKILL to automate large-scale evaluation pipelines and data analysis MS or PhD in electrical engineering 8+ years of experience driving PPA analysis, selection and optimization of foundational IPs - Standard cells and memory compilers in particular Experience owning test chips as chip lead is preferred Experience driving DTCO optimization with foundry partners and design teams on advanced logic technologies is preferred Experience in bringing multiple sub-5nm, 3nm, or 2nm GAA (Gate-All-Around) complex test chips from initial architecture through to validationMeta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics.Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here .Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .