ASIC Engineer, Implementation - Timing

Meta Platforms Inc

  • Austin, TX
  • 5 days ago
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    Skills

    • ASIC (Application Specific Integrated Circuit)unmatched
    • Analysis Skillsunmatched
    • Artificial Intelligence (AI)unmatched
    • Budgetingunmatched
    • Business Growthunmatched
    • Computer Engineeringunmatched
    • Computer Scienceunmatched
    • DFT (Design for Test)unmatched
    • Design Verificationunmatched
    • Electronic Design Automationunmatched
    • Facebookunmatched
    • Logic Designunmatched
    • Network Operations Centerunmatched
    • Noise Analysisunmatched
    • Place and Routeunmatched
    • Scripting (Scripting Languages)unmatched
    • Static Analysisunmatched
    • Static Timing Toolsunmatched
    • System Integration (SI)unmatched
    • Technical/Engineering Designunmatched
    • Timing Verificationunmatched
    • User Interface Designunmatched
    • User Interface Toolsunmatched
    • User Interface/Experience (UI/UX)unmatched
    • Virtual Realityunmatched

    Description

    Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads at scale. As an ASIC Engineer focused on Implementation, you will drive the physical realization of complex custom chips from RTL through tapeout, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will collaborate with architecture, design, and verification teams to deliver high-performance, power-efficient silicon that meets aggressive PPA targets for Meta's next-generation infrastructure platforms.Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes Perform STA for full chip and Physical partition blocks using PrimeTime Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all FE-tools including ( Synthesis, STA) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks Interact with Physical Design Engineers and provide them with timing/congestion feedbackBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience with Timing Analysis Experience with developing full chip flat & hierarchical timing constraints Experience with AOCV/POCV timing analysis , SI noise analysis Experience with running Static Timing Analysis for full chip using DMSA Knowledge of front-end and back-end ASIC flows Experience with communicating across functional internal teams and vendors Experience with SOC Design Integration & Front End Implementation Experience with Back End PD tools such as Fusion Compiler, Innovus Experience with Front End Synthesis tools such as Design Compiler, GenusMeta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics.Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here .Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

    Numbers & Facts

    LocationAustin, TX

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