ASIC/FPGA Methodology Engineer

Job Title: ASIC/FPGA Methodology Engineer
Location: North Reading, MA
Duration: 12 Months Contract (Contract to Permanent)
Pay range: $75.00 to $120.00 per hour on W2

Job Description:
The ASIC/FPGA Methodology Engineer will play a critical role in defining, developing, and maintaining methodologies and workflows for FPGA and ASIC design and verification. The ideal candidate will have a strong foundation in FPGA and embedded design, coupled with expertise in modern development tools in a Linux-based environment. This role requires a proactive individual who thrives in a collaborative environment and is passionate about driving innovation in hardware design.

Responsibilities:

• Develop and maintain methodologies for ASIC/FPGA design, verification, and implementation.
• Collaborate with design and verification teams to ensure seamless integration of workflows and tools.
• Support the development of RTL designs using Verilog and assist in debugging complex hardware issues.
• Optimize design flows for FPGA tools such as Vivado, Quartus, or similar platforms.
• Implement and manage CI/CD pipelines using tools like Jenkins, Docker, and Git to streamline development processes.
• Utilize Linux utilities (e.g., Git, Docker, LSF, Clearcase) to support design and verification workflows.
• Provide technical guidance and training to team members on best practices for FPGA/ASIC methodologies.
• Stay updated on industry trends and emerging technologies to continuously improve design methodologies.

• Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of industry experience in FPGA and embedded design.
• Strong understanding of FPGA and embedded design principles.
• Hands-on experience with FPGA development tools (e.g., Vivado, Quartus).
• Familiarity with ASIC design flows and methodologies.
• Proficiency in utilities such as Git, Docker, LSF, Jenkins, Artifactory, and Clearcase.
• Knowledge of CI/CD workflows and automation tools.
• Understanding of digital design verification methodologies (e.g., SystemVerilog, UVM).
• Experience with timing analysis, synthesis, and timing closure for FPGA/ASIC designs.
• Familiarity with system-level integration and validation.
• Strong problem-solving skills and the ability to debug complex hardware/software issues.