ASIC Physical Design Tools, Flows, Methodologies Manager

ASIC Physical Design Tools, Flows, Methodologies Manager - Google Careers

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ASIC Physical Design Tools, Flows, Methodologies Manager

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Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

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Minimum qualifications:

• Bachelor"s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of experience with the register-transfer level (RTL)-to-GDS process and industry-standard electronic design automation (EDA) tools, including Synopsys, Cadence, and Siemens suites.

• 6 years of experience in a people management role, managing a team of engineers within an application-specific integrated circuit (ASIC) design, semiconductor, or EDA environment.

Preferred qualifications:

• Master"s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience supporting tools, flows, and methodologies (TFM) for ASICs (e.g., artificial intelligence (AI) or machine learning (ML) accelerators) on process nodes.

• Proficiency with scripting and automation languages commonly used in EDA workflows, such as Python, Tcl, Perl, and Make.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google"s most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google"s TPU. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will manage and lead a team of TFM engineers responsible for the physical design flows that power our Tensor Processing Unit (TPU) products. You will guide your team in developing, deploying, and supporting a register-transfer level (RTL)-to-GDS infrastructure. You will bridge design engineering and electronic design automation (EDA) capabilities, balancing resources and managing priorities across projects, feature requests, and bug resolutions to ensure silicon delivery.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google"s product portfolio possible. We"re proud to be our engineers" engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Manage, mentor, and grow a team of tools, flows, and methodologies (TFM) engineers supporting custom silicon development for Tensor Processing Unit (TPU) products.
• Oversee the physical design methodology, driving the development and optimization of flows including place and route (P&R), RC extraction, logic equivalency checking (LEC), static timing analysis (STA), EMIR, and physical verification.
• Triage and manage team priorities across tapeouts, balancing flow bugs, feature developments, and methodology improvements.
• Collaborate with internal physical design (PD) execution teams, register-transfer level (RTL) designers, and external electronic design automation (EDA) vendors to troubleshoot flow issues, improve tool quality of results (QoR), and drive vendor enhancements.
• Define and execute the roadmap for flow automation, runtime efficiency, and scalability across process nodes.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google"s Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google"s EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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