Key Requirements: 10+ years of experience in ASIC/SoC verification and verification architecture. Strong hands-on SystemVerilog, UVM, Verilog, and constrained-random verification. Experience developing verification strategies, test plans, testbenches, coverage models, and verification environments. Strong knowledge of SoC architecture, RTL, CPU/processor, interconnects, memory, and IP verification. Experience with UVM/SystemVerilog assertions, functional/code coverage, simulation, and debugging. Familiarity with C/C++, Python, scripting, formal verification, and emulation is a plus. Experience leading verification teams and working with design, architecture, firmware, and validation teams.
Ideal Candidate: Someone who can own verification architecture from planning → testbench design → implementation → coverage → debug → sign-off.
Numbers & Facts
Location
St louis, MO
Salary
$0–$160 Per Hour
Skills
ASIC Verificationunmatched
Architectural Designunmatched
C Programming Languageunmatched
C++ Programming Languageunmatched
CPU (Central Processing Unit)unmatched
Code Coverageunmatched
Computer Firmwareunmatched
Debugging Skillsunmatched
Formal Verificationunmatched
IP (Internet Protocol)unmatched
Leadershipunmatched
Memory Hardwareunmatched
Model Verificationunmatched
Python Programming/Scripting Languageunmatched
Scripting (Scripting Languages)unmatched
Simulationunmatched
Strategic Planningunmatched
System-on-a-Chip (SoC)unmatched
SystemVerilogunmatched
Team Lead/Managerunmatched
Testingunmatched
Verification Plansunmatched
Verilog Hardware Description Languageunmatched
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