Analysis Skills, Automatic Test Pattern Generation (ATPG), Best Practices, Boundary Scan, Computer Engineering, DFT (Design for Test), Data Analysis, Data Collection, Debugging Skills, Industry Standards, Root Cause Analysis, Scripting (Scripting Languages), System-on-a-Chip (SoC), Tcl-Tk, Test Patterns, Testing
Job Title: Contract Hardware Engineer Mid.
Location: Austin ,TX and Bay Area
Duration: 12 Months
We would prefer someone onsite in Austin ,TX and Bay Area, however we can look at remote candidates as well.
Please specifically check experience on SSM / SSN (Streaming Scan Network) developed by Siemens (Tessent) which Decouples Core (Block) and Chip
Overall experience required : min 8-10 years of relevant exp.
What candidate will Be Doing:
Key Responsibilities:
Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level
Verify test patterns using gate-level simulations.
Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems.
Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing.
Preferred Qualification:
Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG, and MBIST.
Proven experience in developing DFT specifications and architectures for complex designs.
Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage
analysis, and more.
Proficiency in Siemens-Tessent, Client for DFT implementation, vector generation,
and verification.
Ability to conduct experiments during silicon debug, effectively gather and analyze data
to identify root causes.
Efficient scripting skills using TCL for automating tasks and developing custom flows.
Thankse
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