Job Details:
Job Description: Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, lets do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Role Impact: As a Formal Verification Engineer, you will play a pivotal role in ensuring the quality and reliability of Intels cutting-edge CPU technologies. Working as part of the E-Core CPU team, you will leverage formal verification methodologies to develop, implement, and validate the next generation of high-performance CPUs that power a variety of innovative devices, from laptops to AI and machine learning systems. In this role, you will directly impact Intels ability to deliver world-class products that enrich the lives of people across the globe. Join us and help engineer the future at Intel.
Key Responsibilities:
Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications: You must possess a B.S. in Computer Engineering or Electrical Engineering with 3+ years of experience listed below, or a M.S. in Computer Engineering or Electrical Engineering with 2+ years of experience listed below, or a PhD in Computer Engineering or Electrical Engineering with emphasis on formal verification in the following areas:
The experience must include the following areas:
Preferred Qualifications:
Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust: N/A
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during the hiring process, please report this immediately to your recruiter.