CPU Implementation Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldnt have imagined, and now, cant imagine living without. Its the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Austin, Texas. Work extensively with micro-architects to define the micro-architecture, perform design feasibility and do power, performance, and area (PPA) trade-offs. Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA. Design block-level delivery along with closure of backend flows, electrical requirements and improving silicon yield. Work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in CPU design. Work with cross-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability. Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA. 40 hours/week.Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field and 2 years of experience in the job offered or related occupation.

Education and/or experience must include:

Analyzing and figuring out trade-offs for CPU micro-architectural features across performance, area, timing, power, and complexity metrics, providing quantitative assessments to guide architectural decisions to achieve PPA targets within specification. Implementing structured data-path designs using industry-standard synthesis flows, maintaining logic equivalence, performing power intent validation and timing closure through Static Timing Analysis. Generating comprehensive timing constraints for synthesis, PnR, and STA tools supporting multi-GHz designs, ensuring high timing closure success rates and reducing design iteration cycles. Executing floor-planning strategies including hierarchical pin placement and macro positioning for CPU designs, optimizing power grid distribution to achieve IR drop closure while meeting area utilization targets. Applying advanced place-and-route techniques to achieve timing closure on critical paths, while meeting area density targets and optimizing dynamic and leakage power. Developing and executing ECO methodologies to resolve timing violations, noise issues, and EMIR problems. Managing physical design verification flows to achieve zero LVS and DRC violations.N/A