Custom Layout Engineer

MediaTek is a leading global fabless semiconductor company powering more than 2 billion devices a year. Our cutting-edge system-on-chip solutions enable some of the world's most popular smartphones, smart TVs, connectivity products, IoT devices, and more. We combine deep engineering expertise with a collaborative, fast-paced work environment where innovation, curiosity, and teamwork drive everything we do. Our analog/mixed-signal design team is seeking a talented Custom Layout Engineer to join our Austin, TX or San Diego, CA office. The team develops high-performance mixed-signal and custom digital IP that is central to MediaTek's next-generation products. You will collaborate closely with world-class circuit designers and cross-functional partners to deliver robust, high-quality silicon in advanced technology nodes. Position Summary As a Custom Layout Engineer, you will be responsible for creating high-quality custom layout for analog circuits and/or digital standard cells in advanced FinFET and GAA technologies. You will work closely with design engineers to implement high-performance mixed-signal blocks-such as ADCs, DACs, op-amps, bandgap references, flip-flops/latches, and custom digital logic-ensuring that layouts meet stringent performance, area, and reliability requirements. You will own block-level layout design, top-level integration, and the full tape-out verification flow, including DRC, LVS, and DFM checks, as well as updating and improving layouts from previous tape-outs. Key Responsibilities Develop and implement custom layout for analog and mixed-signal blocks, including ADC, DAC, op-amp, bandgap reference, FF/latch, and custom digital circuits. Perform block-level layout design and top-level integration in advanced process technologies (FinFET nodes from ~16 nm to 2 nm). Execute and close full verification flows, including DRC, LVS, DFM, and related checks, to achieve sign-off quality. Analyze and resolve physical design issues, including layout-dependent effects, matching, noise coupling, and complex design rule constraints. Interpret and apply foundry design rules and design reference manuals to ensure compliance at both block and chip-top levels. Update, modify, and optimize existing layouts from prior tape-outs to meet new specifications, performance targets, or technology revisions. * Collaborate closely with circuit design engineers, physical design, and other cross-functional teams throughout the design and tape-out lifecycle.