Datacenter Compute SoC Architect

MediaTek's Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you.

We are seeking a highly experienced and visionary Datacenter Compute SoC Architect to lead the definition, design, and optimization of our next-generation high-performance computing SoCs. In this critical role, you will be responsible for defining the system-on-chip architecture for scalable datacenter processors, balancing Power, Performance, and Area (PPA) constraints while meeting aggressive cloud-scale workloads. You will work cross-functionally with CPU/Compute core architects, IP designers, performance modeling teams, and software/firmware engineers to deliver world-class silicon that powers the future of cloud computing and AI infrastructure.

Key Responsibilities

• SoC Architecture Definition: Lead the architectural definition of next-generation datacenter Compute SoCs, including core/instance counts, cache hierarchies, coherent interconnects, and memory subsystems.
• IP Selection & Integration: Define requirements and drive decisions for third-party and internal IPs (e.g., PCIe Gen 5/6, CXL, DDR5/HBM controllers, Network-on-Chip/NoC, and security enclaves).
• PPA Optimization: Conduct rigorous Power, Performance, and Area (PPA) trade-off analysis to ensure the SoC meets strict datacenter efficiency and performance-per-watt targets.
• Advanced Packaging Strategy: Collaborate with packaging teams on multi-die/chiplet-based architectures, die-to-die (D2D) interconnect protocols (e.g., UCIe), and advanced thermal solutions.
• HW/SW Co-Design: Partner closely with firmware, OS, and cloud infrastructure software teams to ensure the hardware architecture optimally supports modern hypervisors, cloud-native workloads, and virtualization technologies.
• Performance Modeling: Work with the performance modeling team to define use cases, guide the creation of C++/SystemC architectural models, and analyze simulation data to identify bottlenecks.
• Technical Leadership: Write detailed architecture specifications and serve as the technical lead during the RTL implementation, verification, and silicon bring-up phases.

Location: open to San Jose, San Diego, Portland and Austin

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