Home Vacancies Design Engineer – DRAM Design & Technology Co-Optimization (DTCO)Design Engineer – DRAM Design & Technology Co-Optimization (DTCO) Boise, Idaho, USA | Micron Technology, Inc. August 12, 2025Share 0Revolutionizing Memory Through Nanotechnology Join Micron's cutting-edge DRAM Design & Technology Co-Optimization (DTCO) team and be part of engineering the future of semiconductor devices at the nanoscale. This role integrates CMOS circuit design, process integration, and nano-enabled memory architectures to drive the next generation of DRAM technology.Micron Technology seeks a skilled Design Engineer to join its DTCO team, focusing on nanoscale DRAM circuit design, performance optimization, and cross-functional process collaboration. This role is perfect for engineers passionate about semiconductor miniaturization, nanotechnology, and innovative memory solutions.TitleDesign Engineer – DRAM Design & Technology Co-OptimizationOrganization Micron Technology, Inc.Work Location Boise, Idaho, USAResearch Field Nanotechnology, Semiconductor Engineering, DRAM DesignFunding Info Industry-funded, Full-time RoleApplication Deadline Not specified (Apply ASAP)Posted Date RecentCountry United StatesResearcher Profile Experienced Professionals in Circuit & Layout EngineeringRequired Qualification Bachelor's or Master's in Electrical Engineering, Applied Physics, or related fieldRequired Experience CMOS/DRAM process knowledge, simulation tools (Hspice, Finesim), scripting experienceAs a Design Engineer in Micron's DTCO team , you will be at the forefront of nanometer-scale memory design , developing and simulating proxy circuits and blocks that predict and enhance Power-Performance-Area (PPA) for future DRAM products. You'll collaborate across process integration, layout, and design rule teams to ensure optimal nanoscale architecture and manufacturability .Key Responsibilities Develop and evaluate circuit and block-level metrics predictive of product-level PPA.Optimize nanoscale circuit layout for performance, power, and area efficiency .Perform verification and simulation using Hspice, Finesim, and Primesim .Work closely with product design, business units, and process integration teams.Drive innovation in future DRAM generations within a dynamic, high-tech environment.Standardize methodologies and contribute to nanoelectronics design best practices .Required Qualifications Strong knowledge of CMOS circuit design and device physics at the nanoscale.Familiarity with DRAM process technology and I/O design.Experience with memory design and power network analysis .Proficiency in industry-standard simulation tools; Verilog modeling is a plus.Strong scripting skills in Python, Tcl, or Perl .Excellent communication and problem-solving skills.Micron offers a collaborative, innovation-driven work culture with comprehensive benefits including:Medical, dental, and vision coverage optionsPaid family leave and robust paid time-off programsIncome protection and retirement plansOpportunities for career growth in nanotechnology-driven semiconductor designMicron is an Equal Opportunity Employer. Applicants are encouraged to verify job authenticity via the official careers site. AI tools may be used for application enhancement, but misrepresentation will lead to disqualification.NanoHelp.eu connects the global nanotechnology community with conferences, funding, jobs, and research resources. Our mission is to accelerate innovation by bridging academia, industry, and policy in nanoscience.#J-18808-Ljbffr