Summary:
A contract digital design engineer to own integration of the camera ingest path — MIPI C/D PHY and CSI 2 receivers into the image signal processing (ISP) pipeline — including development of the glue logic required to bridge CSI 2 and ISP interfaces.
Duties:
Integrate MIPI C PHY/D PHY, CSI 2 controller and ISP IPs at subsystem and chip level
Design and code the glue logic between CSI 2 output and ISP input: stream/virtual channel handling, data type unpacking, line/frame framing, pixel packing/width conversion, clock domain crossing, backpressure and FIFO/buffering, error and short packet handling
Develop and maintain subsystem μArchitecture and top level RTL; define register maps and configuration/control paths (APB/AHB/AXI)
Drive subsystem/chip level integration and contribute to verification plan development; apply Design for Verification concepts
Extend and maintain our Python based integration/generation tooling (connectivity, register generation, IP assembly, collateral checks)
Support RTL to GDS: constraints, synthesis, timing closure, and low power (UPF) intent for the camera subsystem
Work with FPGA engineers on early prototyping and with validation on bring up, test program support, and chip life to production maturity
Support hand off and integration of blocks into the larger SoC environment
Must Have
4+ years as a Digital Design Engineer, with SoC/subsystem integration ownership
Hands on experience with MIPI C PHY and/or D PHY, CSI 2 protocol, and camera ISP pipelines
Strong Verilog/SystemVerilog RTL coding; digital μArchitecture definition
Demonstrated ability to write new glue/bridge RTL (CDC, flow control, data path packing), not integration only
Python scripting — required, our integration tools are Python based
Tcl scripting; familiarity with synthesis and static timing
Experience with UPF based simulation/low power flows
SystemVerilog UVM/OVM exposure
BS in Electrical/Computer Engineering or Computer Science, or equivalent experience
Knowledge of cameras - experience working in that field
Familiarity with AI assisted code
Nice to Have
MIPI DSI/display, PCIe, USB or other high speed interface experience
ISP algorithm/pipeline analysis; fixed point data path understanding
PHY/controller IP vendor deliverable bring up and PPI/lane management debug
DFT/testability and test program definition; Power Aware GLS
FPGA prototyping; Tensilica DSP/TIE
MSEE/CS
Education:
Bachelor's in Eng. required.
Shift:
Remote/Hybrid.
About US Tech Solutions: US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.
US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.
#LI-AS140
Numbers & Facts
Location
Burlingame, CA (Remote)
Salary
$70–$150 Per Hour
Skills
Algorithmsunmatched
Analysis Skillsunmatched
Artificial Intelligence (AI)unmatched
Centers for Disease Control and Prevention (CDC)unmatched
Change Controlunmatched
Computer Engineeringunmatched
Computer Scienceunmatched
DFT (Design for Test)unmatched
Debugging Skillsunmatched
Design Verificationunmatched
Electrical Engineeringunmatched
FIFOunmatched
FPGAunmatched
Financial Controlunmatched
Graphic Designunmatched
IP (Internet Protocol)unmatched
Image Processingunmatched
Input/Outputunmatched
Internet Service Providersunmatched
Intrusion Prevention Systemsunmatched
Low Powerunmatched
Machine Toolunmatched
PCI Express (PCI-E)unmatched
PHYunmatched
Producer Price Index (PPI)unmatched
Prototypingunmatched
Python Programming/Scripting Languageunmatched
RTL Designunmatched
Receiversunmatched
Scripting (Scripting Languages)unmatched
Semiconductor Manufacturingunmatched
Signal Processingunmatched
Simulationunmatched
Static Timing Toolsunmatched
System Architectureunmatched
System Integration (SI)unmatched
System-on-a-Chip (SoC)unmatched
SystemVerilogunmatched
Systems Maintenanceunmatched
Tcl-Tkunmatched
Technical/Engineering Designunmatched
Test Programunmatched
Testabilityunmatched
Timing Verificationunmatched
USBunmatched
Verification Plansunmatched
Verilog Hardware Description Languageunmatched
Writing Skillsunmatched
🎯
Be found by employers
5,500+ employers search our resume database daily. Add yours to get found by recruiters looking for candidates like you.
Level up your application
Professional resume templates
Browse dozens of recruiter approved resume templates, layouts and formats. Choose your favorite and make it your own in minutes.