$178,500–$331,500 Per Year
Architectural Design, Architectural Services, Cadence, Communication Skills, Compensation and Benefits, Computer Engineering, Customer Support/Service, Dental Insurance, Design Verification, Electrical Engineering, Electricity, I/O Circuits, IP (Internet Protocol), Intrusion Prevention Systems, Joint Electron Device Engineering Council (JEDEC), Memory Hardware, Outbound Marketing, PHY, Presentation/Verbal Skills, Product Planning, Regulatory Compliance, Sales, Signal Integrity, Stock Purchase Plans, Technical Writing, Technical/Engineering Design, Vision Plan, Writing Skills
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Design Engineering Architect - Roles & Responsibilities
- Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations
- Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements
- Good understanding of PHY/IO circuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offs
- Act as a customer‑facing technical architect during pre‑sales, evaluations, and post‑delivery support, clearly articulating architecture choices and trade‑offs
- Collaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposals
- Provide expert‑level IP support to customers, including architecture clarification, feature customization
- Work cross‑functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implemented
- Review and guide architecture specifications, design reviews, and technical documentation
- Influence product and technology roadmap planning by identifying future standards, protocol evolution, and customer‑driven requirements
- Demonstrate strong communication, accountability, and technical ownership across internal and external interactions
Required Qualifications
- M.S. degree in Electrical Engineering, Computer Engineering, or related field
- Minimum 15 years of industry experience in memory interface PHY, high‑speed IO, or related domains
- Strong background in memory interface PHYs, JEDEC standards, and protocols
- Proven ability to own customer‑facing technical engagements and drive issues to closure
- Excellent written and verbal communication skills
The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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Cadence Design Systems Inc