Design Verification

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldnt have imagined, and now, cant imagine living without. Its the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with RTL designers and architects to understand and review specifications and architecture and extract features as part of the verification team supporting Apples Display Technologies portfolio for the next-generation of Apple products. Develop verification strategies, including test plans and coverage requirements to cover the functional and performance requirements of the design. Design, implement, and maintain scalable and re-usable SystemVerilog UVM based test-benches for SOC and sub-system level verification. Update environment scripts (Python) to support new test configurations. Write and maintain test cases using directed/constrained random test generation and assertion-and formal-based verification. Create coverage models and tracking coverage metrics to ensure 100% coverage goals are met. Run RTL and gate-level simulations investigating failures from daily/nightly simulations run at chip/block level, using log analysis and waveform tools (lndago/SimVision) to review them with the RTL designers and file bug reports as appropriate. Build and maintain automated regressions; Coordinate with architects/designers for end-to-end validation; Create and maintain up-to-date documentation for test plans, attributes, and verification environment. Support scripted automation flows as needed to enhance the verification methodology. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.Master's degree or foreign equivalent in Electrical and Computer Engineering or related field. Experience and/or education must include:

Using Verilog and SystemVerilog for testbench and constrained random test development to build the verification infrastructure. Testplan and coverage plan development in order to plan the test scenarios and the features that need to be covered. Using C or C++ to be used for reference model or checker development to check the correctness of the design behavior. Perl, Python, or tcl scripting to set up the regression automation flow which facilitates running test suites. Knowledge of Digital Electronics and RTL design concepts to understand the design microarchitecture. Experience with simulators and waveform viewers for running tests, debugging digital designs and finding bugs. Understanding and knowledge of writing System Verilog Assertions (SVA) for simulations-based and formal verification to be used for checker development.N/A