We are seeking a Senior Formal Verification Engineer with 8–10+ years of experience in semiconductor design verification and a strong focus on formal verification methodologies. The ideal candidate will have hands-on experience with Synopsys VC Formal and/or Cadence JasperGold, strong expertise in SystemVerilog Assertions (SVA) and formal property specification, and experience with FPV, connectivity checking, register verification, equivalence checking, and coverage analysis. The candidate should also be proficient in SystemVerilog, UVM, and scripting languages such as TCL, Python, or Perl for verification flow automation.
Must-Have Skills:
| Location | Austin, TX |
| Job Type | Contractor |
| Industry | Staffing/Employment Agencies |
| Salary | $75–$80 Per Hour |
| Year Founded | 1998 |
| Headquarters | Birmingham, Alabama, US |
| Website | https://www.tpiglobalsolutions.com/ |
TPI started in 1998, providing technical professionals to businesses scrambling to fix the Y2K bug. We met those challenges head-on and established ourselves as an IT talent and services firm that could be counted upon.
Since then we’ve grown. We continue to connect employers with tough-to-find IT expertise and help technical professionals find jobs that match their career goals. Now we are doing the same with engineering, finance and accounting professionals from our Birmingham, Atlanta and Charlotte offices.
As one of the top engineering and IT recruiting firms in the country, we know what it takes to find the right people for the job. Building a talent network from professionals nationwide – people with tons of skills and experience in information technology, engineering, accounting & finance and more.
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