Design Verification Engineer

Design Verification Engineer, Principal

Location

Santa Clara, CA

Work Arrangement

Onsite

Employment Type:

Full-Time (Permanent)

Salary:

$158,600 – $317,800 per year

About the Organization

Our client is a global leader in semiconductor and infrastructure technology, designing advanced chip solutions that power high-performance computing, networking, telecommunications, and data center systems worldwide.

The organization is at the forefront of innovation in high-speed data transfer, networking architectures, and system-on-chip (SoC) design. Its solutions are widely used across enterprise, telecom, cloud, automotive, and AI-driven industries.

With a strong focus on engineering excellence, cutting-edge research, and product reliability, the company provides an environment where engineers work on complex, large-scale systems that directly impact next-generation technologies.

Position Overview

We are seeking a

Principal Design Verification Engineer

to join a high-performing engineering team focused on advanced networking and SoC verification.

This role involves developing and leading functional verification environments for complex semiconductor designs, ensuring high-quality, scalable, and robust chip validation. The ideal candidate will bring deep technical expertise in verification methodologies, strong leadership experience, and the ability to work closely with design and architecture teams in a fast-paced development environment.

You will contribute to verification strategy, test planning, environment development, debugging, and cross-functional engineering collaboration.

Key Responsibilities

Verification Planning

Execution

Develop detailed verification test plans using constrained-random and coverage-driven methodologies.

Work closely with design teams to ensure completeness of verification requirements.

Define and track functional coverage metrics to ensure design quality.

Environment Development

Architect and build advanced verification environments using SystemVerilog and UVM.

Develop bus-functional models, reference models, drivers, and monitors.

Create scalable and reusable verification components.

Debugging

Validation

Develop and execute directed and random test cases.

Debug functional failures and collaborate with design engineers to resolve issues.

Perform root cause analysis of complex system-level issues.

Tool

Methodology Development

Develop tools and scripts to enhance verification efficiency and automation.

Work on regression testing frameworks and verification infrastructure.

Support development of scalable tools for multi-core SoC environments.

Software

Firmware Validation

Verify boot code and assist in firmware/software validation.

Develop tools and frameworks in C++, Python, or Perl for verification automation.

Support unit and regression testing of internal tools.

Leadership

Collaboration

Lead or contribute to verification efforts on complex SoC projects.

Work with cross-functional teams including design, architecture, and software engineering.

Contribute to project planning and execution under tight tape-out schedules.

Provide technical guidance to junior engineers where applicable.

Required Qualifications

Education

Experience

Bachelor’s degree in Computer Engineering, Electrical Engineering, or Computer Science.

10+ years of experience in design verification, OR

Master’s/PhD with 5+ years of relevant experience.

Technical Skills

Strong expertise in SystemVerilog and UVM.

Experience building complex constrained-random verification environments.

Strong understanding of functional coverage and test planning methodologies.

Experience with scripting languages such as Python or Perl.

Experience with EDA verification tools.

Strong object-oriented design and programming skills.

Additional Technical Experience

Proficiency in C++ programming.

Understanding of Linux operating systems.

Exposure to ARM architecture and assembly language is a plus.

Knowledge of networking protocols is preferred.

Leadership

Soft Skills

Proven ability to lead verification efforts for complex SoC projects.

Strong debugging and problem-solving skills.

Ability to work independently in fast-paced environments.

Open-minded, collaborative, and adaptable engineering approach.

Strong communication skills and ability to work across teams.

Compensation

Benefits

Competitive salary:

$158,600 – $317,800 annually

Full benefits package (medical, dental, vision, etc.)

Retirement and equity programs (as applicable)

Opportunity to work on cutting-edge semiconductor technologies

Exposure to large-scale, global engineering projects

High-impact role with technical leadership responsibilities

Why Join?

Work on next-generation semiconductor and networking technologies.

Contribute to high-performance SoC designs used globally.

Join a world-class engineering organization with strong technical depth.

Opportunity to lead and influence verification architecture and methodology.

Work in a fast-paced, innovation-driven environment focused on advanced chip design.