About the role
We are looking for an experienced DFT Architect to lead Design-for-Test strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes. The ideal candidate will drive end-to-end DFT architecture including scan with compression technologies, MBIST, boundary scan, SSN architecture, functional testing and at-speed test methodologies while collaborating with cross-functional teams to achieve high test coverage, quality, and silicon bring-up success.
What you'll do
- Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs.
- Lead implementation of scan insertion, ATPG, MBIST, boundary scan, SSN implementation, and test compression methodologies.
- Drive DFT planning and integration aligned with power, timing, area, and test coverage goals.
- Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff.
- Analyze and resolve DFT-related timing, routing, and testability challenges.
- Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization.
- Develop and enhance DFT automation flows, methodologies, and reusable infrastructure.
- Mentor junior engineers and provide technical leadership across projects.
WhatWe’reLooking For
- Bachelor’s orMaster’sdegree in Electronics, Electrical Engineering, VLSI, or related field.
- 10+ years of experience in ASIC/SOC DFT implementation and architecture.
- Strongexpertisein scan, ATPG, MBIST, JTAG, compression, and low-power DFT methodologies.
- Hands-on experience with industry-standard DFT tools such as SiemensTessent, Synopsys DFT Compiler/TestMAX, or equivalent.
- Strong understanding of RTL design, timing, physical design constraints, and silicon debug.
- Experience with advanced technology nodes and large SOC integration.
- Strong scripting and automation skills usingTcl, Python, Perl, or Shell.
- Excellent leadership, problem-solving, and cross-functional collaboration skills.
Good to Have
- Experience with automotive safety standards such as ISO 26262.
- Exposure to chiplet-based architectures and 3D IC testing methodologies.
- Knowledge of diagnosis-driven yield improvement and silicon analytics.
Success in This Role Looks Like
- Delivery of robust DFT architectures with high test coverage and efficient manufacturing test cost.
- Successful silicon bring-up with minimal DFT-related issues.
- Improved DFTmethodologyscalability, automation, and execution efficiency.
- Strong technical leadership and contribution to organization-wide DFT best practices.
Compensation
The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.
In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.