Job Description
Job Title: DFT Engineer
Location: Santa Clara, CA
Work Arrangement: Onsite
Experience: 5+ Years
JOB DESCRIPTION
We are seeking an experienced DFT Engineer to join a cutting-edge Silicon Engineering team working on next-generation GPU and AI products. The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug.
This is an excellent opportunity for a hands-on DFT Engineer to contribute to complex ASIC/SoC designs and next-generation semiconductor products.
Job Responsibilities
KEY RESPONSIBILITIES
* Design and implement DFT architectures for complex ASIC/SoC designs.
* Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.
* Develop and execute ATPG patterns and perform fault simulation and test coverage analysis.
* Analyze and improve test coverage, test quality, and DFT implementation.
* Support silicon bring-up, post-silicon debug, failure analysis, and production test activities.
* Work closely with Design, Verification, Physical Design, Product Engineering, and other cross-functional teams.
* Participate in DFT implementation, verification, and signoff activities.
* Debug DFT-related issues across pre-silicon and post-silicon environments.
* Contribute to DFT methodologies, automation, and process improvements.
* Support the transition of DFT solutions from design through silicon validation and production.
Numbers & Facts
| Location | Santa Clara, CA |
| Job Type | Contractor, Full-time |
| Salary | $50–$90 Per Hour |
| Company Size | 201 - 500 |
| Headquarters | Livonia, MI, US |
| Website | https://plugins-inc.com/ |
Qualifications
REQUIRED QUALIFICATIONS
* 5+ years of hands-on experience in DFT engineering.
* Strong understanding of DFT architecture and methodologies for ASIC/SoC designs.
* Strong hands-on experience with:
. Scan
. Scan Compression
. MBIST
. LBIST
. ATPG
. JTAG
. IJTAG
* Strong knowledge of IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.
* Experience with fault simulation and test coverage analysis.
* Proficiency in Verilog and/or SystemVerilog.
* Strong scripting/programming skills using Python, Perl, TCL, and/or Shell.
* Experience with one or more industry-standard DFT tools, such as:
. Synopsys TestMAX
. Synopsys DFT Compiler
. Siemens Tessent
. Cadence Modus
PREFERRED QUALIFICATIONS
* Experience with complex ASIC/SoC design environments.
* Experience working on GPU, AI, CPU, or other high-performance silicon products.
* Strong silicon bring-up and post-silicon debug experience.
* Experience with production test and test engineering methodologies.
* Experience collaborating across Design, Verification, Physical Design, and Product Engineering teams.
* Strong problem-solving and communication skills.
KEY SKILLS
DFT | Design for Test | ASIC | SoC | Scan | Scan Compression | MBIST | LBIST | ATPG | JTAG | IJTAG | IEEE 1149.1 | IEEE 1500 | IEEE 1687 | Fault Simulation | Test Coverage | Silicon Bring-Up | Silicon Debug | Verilog | SystemVerilog | Python | Perl | TCL | Shell | Synopsys TestMAX | DFT Compiler | Siemens Tessent | Cadence Modus
Skills
- ASIC Designunmatched
- Artificial Intelligence (AI)unmatched
- Automatic Test Pattern Generation (ATPG)unmatched
- Boundary Scanunmatched
- DFT (Design for Test)unmatched
- Debugging Skillsunmatched
- GPU (Graphics Processing Unit)unmatched
- Semiconductorsunmatched
- System-on-a-Chip (SoC)unmatched
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