DFT Engineer

Position Overview\n

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As a Senior DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting, and executing robust Design-for-Test strategies for high-performance SoCs/ASICs. You will work closely with front-end design, physical design, verification, and product engineering teams to ensure high test coverage, optimal silicon quality, and streamlined post-silicon manufacturing test enablement.

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Key Responsibilities\n

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• Pre-Silicon Execution:
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• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG / IEEE standards (1149.1, 1500, 1687 IJTAG).
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• Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.
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• Integrate Memory BIST (MBIST) controllers, repair mechanisms, and custom memory test routines.
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• Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, including Stuck-at, At-Speed (Transition/Path Delay), and Cell-Aware testing.
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• Execute Verilog/SystemVerilog simulations for gate-level DFT validation, ensuring timing and vector cleanliness (SDF simulation).
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• Run DFT linting and rule checking using industry-standard tools (e.g., SpyGlass DFT, Tessent, Modus, or TetraMAX)
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• Post-Silicon Production & Bring-up:
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• Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) for ATE (Automatic Test Equipment) deployment.
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• Support post-silicon bring-up in the lab, debugging first-silicon DFT features, pattern conversion, and silicon failures.
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• Collaborate with Product and Test Engineering (PTE) teams to optimize test time, diagnose failure modes, and boost manufacturing yield.
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Required Qualifications\n

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• Experience: 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes.
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• Core Skills & Technical Expertise:
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• Verilog / SystemVerilog: Strong proficiency in Hardware Description Languages for DFT integration, wrapper creation, and simulation debugging.
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• Scan Insertion: Hands-on experience with scan synthesis, compressed scan architectures (EDT/SmartTest), and boundary scan integration.
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• ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
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• MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
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• JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
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• Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.
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• ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
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• MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
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• JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
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• Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.
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Preferred Skills\n

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• Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.
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• Knowledge of advanced DFT concepts like High-Speed IO testing, SerDes loopback, or Analog DFT.
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• Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes.
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