Job Description
New 3-year contract Digital Design Engineer
Pay Range: $75-$105/hr.
Hybrid: 60% onsite
Clearance: eligible for Secret
The Tactical Edge Communications Group specializes in advanced network and communications systems development, with a focus on rapid prototyping of radical next generation tactical mobile, military airborne communications systems.
Pay Range: $75-$105/hr.
Hybrid: 60% onsite
Clearance: eligible for Secret
The Tactical Edge Communications Group specializes in advanced network and communications systems development, with a focus on rapid prototyping of radical next generation tactical mobile, military airborne communications systems.
| The Tactical Edge Communications Group is seeking to hire a digital design engineer that will develop digital signal processing blocks in VHDL for use in wireless communications systems. The group is developing novel new architectures and waveforms and is looking to add to the team that will prototype and field-test the technologies. Required Skills: 1. Strong VHDL (preferred)/Verilog firmware development experience to include VHDL development, simulation, synthesis, and timing closure A skills test will be given to potential candidates 2. Strong experience with Xilinx FPGAs, Zynq SoC architectures, and Vivado 3. Experience with Rapid software prototyping VHDL code 4. Experience with scripting languages (TCL, Bash, Python, etc) 5. Experience with lab equipment (oscilloscopes, logic analyzers, etc) 6. Experience with revision control (GIT) 7. Experience with embedded SoC architectures (DSP + ARM) and embedded software (DMA interface, etc) 8. Strong Matlab analysis skills tailored to wireless digital communications and using it as a golden model 9. Experience implementing DoD waveforms 10. Signal processing experience, in particular turbo encoders and decoders Preferred Skills: 1. Strong understanding of fundamentals of wireless digital communications systems and all PHY processes from data in to baseband I/Q out Be able to clearly articulate the function of all digital blocks in a typical communications chain (encoders, modulators, correlators, etc.). Preference will be given to candidates who have implemented and deployed real systems 2. Experience integrating FPGA code into infrastructure and hardware to include JESD-204B interfaces Education: Bachelor's degree required. -Interim clearance is acceptable for the start of the position -This position will be onsite 60% and remote 40% of the time. Onsite vs remote capabilities may fluctuate with project demands. Candidate should be local to Lexington for the start of the position. -Interview process will be two round of interviews via Zoom. |
| Must Have | |
|---|---|
| Degree Level | |
| Bachelor's Degree | Yes |
| Design | |
| Experience creating and maintaining accurate and detailed design files | 6 years |
| Experience with complex, high-speed HDL based implementations of algorithms | 6 years |
| Electrical/Electronics | |
| Xilinx FPGA | 6 years |
| Xilinx RFSoC experience | 3 years |
| Experience | |
| Test equipment (oscilloscopes, signal generators, logic analyzers, power supplies, data acquisition) | 6 years |
| Hardware | |
| Firmware | 6 years |
| Hardware Design | 6 years |
| Programming | |
| FPGA Programming | 6 years |
| VHDL / Verilog | 6 years |
| Signal Processing | |
| Digital Signal Processing (Analysis and/or Implementation) | 3 years |
| Software | |
| Configuration Management Tools (GIT, SVN) | 6 years |
| Software Tools | |
| Vivado Software Experience | 6 years |
| Systems | |
| System Simulation | 6 years |
| Nice to Have | |
| Experience | |
| Currently holds a Secret Clearance (OR a higher clearance) | Yes |
Numbers & Facts
| Location | Bedford, MA |
| Industry | Staffing/Employment Agencies |
| Salary | $75–$105 Per Hour |
| Company Size | 500 to 999 employees |
| Year Founded | 1999 |
| Website | https://www.csetalent.com/ |
About Company
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