Digital Mixed Signal Modeling Engineer

Join our team at Apple developing the mixed-signal PMU ASICs at the heart of Apple's hardware products. PMUs contain mixed-signal functions such as throttling, system telemetry collection and processing, and a range of high-performance and high-efficiency power conversion blocks - including buck converters, LDOs, charge pumps, and voltage references - that have enabled Apple products' industry-leading battery life. As a member of our mixed-signal ASIC team, you will design, develop, and validate SystemVerilog real-number models of complex analog IPs that interface with digital control blocks. Your models will close the loop in digital mixed-signal simulations, helping find bugs in both the digital and analog portions of the design before silicon.

The PMU Digital Mixed Signal (DMS) team has a unique opportunity for engineers looking for a role that bridges digital and analog design. DMS engineers work closely with analog and digital designers to create SystemVerilog real-number models (RNM) of analog circuits, capturing key behaviors such as DC-DC converter regulation, overshoot/undershoot and ripples. These models are essential for high-speed digital/analog closed-loop simulations that typically run more than 100x faster than schematic-based simulations, providing vital productivity gains across the project lifecycle.

DMS simulations have been foundational to the PMU team's track record of meeting aggressive schedules while delivering industry-leading power converters. You will work at the intersection of analog and digital design - reading schematics, attending architecture and design reviews, building and debugging models, and correlating results against transistor-level simulations. In this role, you will gain deep exposure to full-chip integration, tapeout cycles, and silicon bring-up correlation across Apple's broad product portfolio.

Partner with analog designers to define model specifications, including transfer functions, timing behavior, non-idealities, and operating ranges

Develop SystemVerilog real-number models from analog schematics and design specifications

Verify models by model versus schematic simulations, and root-cause any mismatches

Create SystemVerilog testbenches for standalone model validation

Integrate models into full-chip DMS simulation environments in support of digital and analog mixed-signal verification teams

Maintain and evolve model libraries across project generations, ensuring accuracy and reusability

Develop model accuracy metrics and regression suites to track model quality over time

Participate in design reviews and architecture trade-off discussions with analog and digital teams

Automate modeling and analysis workflows using Python or similar scripting languages

A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience.

Solid understanding of both digital and analog circuit fundamentals

Proficiency in Verilog or SystemVerilog

Ability to read and interpret analog schematics and simulation results

Excellent communication and cross-functional collaboration skills

• Experience with SystemVerilog real-number modeling (RNM) or wreal/EEnet methodology

• Hands-on experience with power management circuits such as LDOs, buck converters, charge pumps, or voltage references

• Familiarity with digital verification methodology (e.g., UVM, coverage-driven verification)

• Experience with mixed-signal or digital simulation tools (e.g., Xcelium, Virtuoso)

• Proficiency in Python or similar scripting for automation and analysis

• Experience using LLM-based or AI-assisted coding tools for model or RTL development