Digital Verification Engineer

Digital Verification Engineer

3 Year Contrat

Pay Range: $85-$105/hr

5 days onsite

Clearance: Interim clearance is sufficient for the start of this assignment, however ACTIVE SECRET is HIGHLY preferred.

The Tactical Edge Communications Group is seeking eager candidates to develop and verify FPGA to support prototyping, lab experimentation, and field experimentation of novel communications and sensing applications.

Required Skills:
• Bachelor’s degree, Master’s degree, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Mathematics, Physics, or related scientific/engineering field
• Strong knowledge of hardware description languages including VHDL, Verilog, and/or System Verilog
• Experience designing and testing programmable logic designs targeting System on Chip (SoC) FPGA architectures that required integration of the programmable logic with on-chip software processing
• Experience with unit-level and FPGA chip level verification of RTL
• Experience with laboratory benchtop testing of FPGA designs including the use of integrated logic analyzers (e.g. ChipScope) and/or laboratory equipment such as stand-alone logic analyzers or digital oscilloscopes
• Experience designing, testing, and debugging high-speed I/O interfaces and protocols utilizing an FPGA’s built-in SERDES
• Experiencing developing, designing, and programmable logic for signal processing applications
• Strong verbal and written communications skills including collaborating with other on-site and/or remote technical team members, preparing and sharing technical results with others, and documenting work to aid other team members and activities

Desired Skills:
• Experience developing and testing with Xilinx-based RFSoC devices
• Experience using Modelsim/Questa/CocoTB toolchain for RTL simulation
• Familiarity with continuous integration (CI) pipelines for joint FPGA and embedded software development
• Familiarity with Ethernet, Infiniband, and/or PCIe protocols, testing, tools, and debugging
• Familiarity with RDMA and RoCE protocols
• Experience programming in Python

-Candidate should expect to be onsite 5 days/week due to the nature of the work. Candidates expected to be local at the start of the assignment.
-Interim clearance is sufficient for the start of this assignment, however ACTIVE SECRET is HIGHLY preferred.

 

Degree Level
Bachelor's Degree	Yes
Design
Experience with design/HDL analysis, including high speed and low power design	5 years
Engineering
Experience developing hardware verification plans	5 years
Experience performing hardware verification and material compatibility testing	5 years
Validates that digital design meets specifications	5 years
Experience
Verification engineering experience to support design teams	5 years
Programming
FPGA Development (VHDL/Verilog or SystemVerilog)	5 years
Signal Processing
Digital Signal Processing	3 years
Software Tools
Chip-Level Debugging tools (Chipscope/Signal Tap)	5 years
Nice to Have
Electrical/Electronics
Xilinx RFSoC experience	0 years
Programming
Python Programming/Scripting	0 years
Software Tools
Simulation Tools (ModelSim/Questa)	0 years