WHAT YOU'LL DO Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designsDevelop verification plans with traceability to system and hardware requirementsAuthor SystemVerilog Assertions (SVA) for protocol compliance and design intent checksBuild functional coverage models and drive code coverage analysis to closureDevelop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugsEstablish and maintain regression suites, tracking coverage metrics and verification progressDebug failures using waveform tools and simulation logs at the HDL and system levelCollaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinementSupport hardware validation and board bring-up on target platformsEnsure verification meets DO-254 and relevant safety standardsAuthor verification closure reports and coverage analysis summariesREQUIRED QUALIFICATIONS Bachelor\'s degree in Electrical Engineering, Computer Engineering, or related field2+ years of experience in FPGA/ASIC verificationProficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenchesObject-oriented programming principlesIndustry simulators (Questa, VCS, Xcelium, or Vivado)Git-based collaborative workflows including code reviewLinux development environmentsStrong communication and teamwork skillsEligible to obtain and hold a U.S. Secret security clearancePREFERRED QUALIFICATIONS 5+ years of experience in FPGA/ASIC verificationMaster\'s degree in Electrical Engineering, Computer Engineering, or related fieldDO-254, avionics verification standards for UAS, and safety-critical verification processesSVUnit or equivalent unit-testing frameworksFormal verification or CDC verification toolsDigital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPIVerification automation scripting (Python, Tcl, Makefile)SoC and ARM-based embedded platformsVerification automation, CI/CD integration, and Nix-based build environments#J-18808-Ljbffr
| Location | Costa Mesa, CA |