Hardware Design Engineer 2

Job Overview:

Pay Range: $60.71hr - $65.00hr

Requirement/Must Have:

• Digital design engineering experience.
• Experienced with Verilog, System Verilog, C, and C++.
• Excellent knowledge of Verilog, System Verilog and a scripting language.
• Knowledge of clocking architectures, synchronization, and CDC methodology.
• Experience with synthesis and timing closure.
• Strong understanding of computer organization/architecture.
• Bachelors or Masters degree in Computer Engineering or Electrical Engineering.

Responsibilities:

• Perform RTL design for memory I/O PHY.
• Develop Digital Architecture from pathfinding, coding, and verification to physical implementation.
• Execute PHY link layer design, implementation, and verification with Analog and System architects.
• Perform PHY Analog/Digital co-design.
• Conduct digital design and RTL coding.
• Manage Timing Synthesis and drive physical implementation.
• Collaborate with architects, hardware engineers, and firmware engineers to understand new features to be verified.
• Estimate time required for new feature tests and required changes to the test environment.
• Build unit tests.
• Debug design failures to determine root cause and work with DV and firmware engineers to resolve defects.

Nice to Have:

• Experience with Python, Perl, and TCL.
• SERDES, DDR, Memory Controller, or MAC Design experience.
• Mixed signal RTL and Low power design experience.
• Exposure to leadership or mentorship.

Skills:

• RTL Design.
• Verilog.
• System Verilog.
• C.
• C++.
• Python.
• Perl.
• TCL.
• Timing Synthesis.
• LPDDR.
• DDR IP.
• Memory PHY.
• Digital Architecture.

Qualification And Education:

• Strong analytical and problem-solving skills.
• Strong verbal and written communication skills.
• Ability to communicate effectively with stakeholders.
• Team player with experience collaborating across different sites and timezones.