Hardware Design Engineer 5

Job Title:   Hardware Design Engineer 5
Location:   Remote ( preferred PST  Time Zone )
Salary Range:  $95/hr to $100/hr on W2

Introduction

Join a dynamic team focused on hardware design verification for accelerated network IP, where you will ensure features are fully validated through comprehensive test coverage. As a verification engineer, you will contribute to the verification efforts for accelerated networking hardware, including executing and validating test plans within an existing System Verilog and UVM environment.

Required Skills & Qualifications

• 10 years of technical engineering experience with hardware design verification
• 10 years of experience with verification methodologies
• 10 years of experience with System Verilog
• Experience in hardware design verification and methodologies
• Solid RTL understanding
• Execute the test plan by adding test cases and tracking verification through coverage-driven metrics
• Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage
• Experience executing test plans, debugging, and validating scenarios
• Prior work experience at the client or in the client's industry
• Applicants must be able to work directly for Artech on W2

Preferred Skills & Qualifications

• Experience in hardware design verification and methodologies
• Solid RTL understanding
• Experience executing test plans, debugging, and validating scenarios

Day-to-Day Responsibilities

• Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams
• Execute the test plan by adding test cases and tracking verification through coverage-driven metrics
• Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage
• Script to automate and maintain execution of test suites to support continuous integration (CI) and continuous development (CD) flow
• Apply Agile development methodologies such as hosting code reviews, sprint planning, frequent deployment to cloud, and iterative development of features

Company Benefits & Culture

• Opportunity to work on the largest deployment of FPGA SmartNICs (Azure Boost) in the world
• Develop infrastructure for next-generation Software-Defined Networking (SDN)
• Enhance network security and improve performance with Remote Direct Memory Access (RDMA) and custom network protocols

For immediate consideration please click APPLY to begin the screening process with Alex.