Layout Principal Designer

This SkyWater Layout Principal Designer will primarily lead custom layout and Electronic Design Automation (EDA) activities to provide testchip collateral for semiconductor integrated circuit (IC) technologies. This engineer will be a significant contributor to a broad array of design projects supporting modeling, reliability, and yield as part of Process Design Kit (PDK) development for advanced CMOS or quantum technologies.The position is based at our HQ site in Bloomington, MN, with consideration available for remote work.Major Areas of Accountability:

Layout of new structures for eTest, modeling, reliability, yield, and IP testchips as part of new technology developmentVersion control and management of large design libraries with multiple contributorsIntroduction of both custom and automated designs for both new & derivative layout projects supporting highly diverse technology flowsUtilize SkyWater PDK's and provide feedback to internal teams on issues, improvements, capabilities, etc.Lead physical verification and tape-in reviews

Required Qualifications:

Expert in custom layout design using IC EDA tool-assisted design flow such as Cadence and Siemens EDA tool suites, (e.g. Calibre and Virtuoso)Familiarity with layout automation using SKILL, Tcl, python or other scripting languages.Knowledge and experience in developing and/or using physical verification tools (DRC, ERC, LVS/PEX) and DFM tooling.Experience in IP project and/or library management.Familiarity with typical mixed-signal IC design.Clear communicator, concise written report skills, and inventive problem solverU.S. Person Required: This position requires compliance with the International Traffic in Arms Regulations (ITAR). All accepted applicants must be U.S. Persons.ITAR defines a U.S. Person as U.S. citizen, U.S. Permanent Resident, Political Asylee, or Refugee.7 - 10 years of experience with AS in Electronic Design fields. 5-7 years of experience with BS in Electrical Engineering, Microelectronics or related fields.

Preferred Qualifications:

Background in PDK development in some or all of the following fields: CMOS, MEMS, photonics, and superconducting.Familiarity with parasitic extraction tools such as Mentor Calibre xRC, Cadence Quantus, or Synopsys StarRC.Experience in project management of IC design (architecture to GDS) & fabrication (tape-out to post-silicon validation and testing).Experience with chemical-mechanical polishing (CMP) shape density filling techniques.Experience with data preparation and/or OPC methodologies.