Cadence, located in Austin, Texas, is seeking a Design Verification expert to lead subsystem and SOC verification efforts. Ideal candidates will have extensive experience with SV-UVM, ARM designs, and mentoring capabilities.The role requires strong problem-solving abilities and a systematic approach to verification. Successful candidates will contribute significantly in a fast-paced environment, ensuring high-quality deliverables.If you are passionate about making an impact in technology, join us at Cadence!#J-18808-Ljbffr