Mixed-Signal Behavioral Modeling Engineer

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    Skills

    • Analog Circuit Designunmatched
    • Artificial Intelligence (AI)unmatched
    • Automationunmatched
    • Cadenceunmatched
    • Cloud Computingunmatched
    • Communication Skillsunmatched
    • Debugging Skillsunmatched
    • Design Verificationunmatched
    • Digital Signal Processing (DSP)unmatched
    • EADunmatched
    • Graphic Designunmatched
    • Metricsunmatched
    • Network Operations Centerunmatched
    • Scalable System Developmentunmatched
    • Schematicsunmatched
    • Semiconductorsunmatched
    • SystemVerilogunmatched
    • Test Plan/Scheduleunmatched
    • Testingunmatched
    • Verification Plansunmatched
    • Verilog Hardware Description Languageunmatched
    • Waveformsunmatched
    • Writing Skillsunmatched

    Description

    Mixed‑Signal Behavioral Modeling EngineerFull‑time, Onsite (Austin, Texas). 5+ years of experience. Employment Type: Direct Hire (Core Team). Sponsorship: Likely H1B/EAD eligible.Our client is a Series‑D semiconductor innovator specializing in programmable coherent DSP solutions powering cloud and AI infrastructure. Their breakthrough DSP technology is foundational to high‑speed data center interconnects, enabling faster, more efficient cloud and AI communications.Job OverviewThe role focuses on mixed‑signal verification for advanced DSP‑based communication and AI interconnect chips. You'll develop behavioral models for analog blocks, run mixed‑signal dynamic verification, and collaborate with world‑class analog and digital design teams to validate next‑gen coherent DSP solutions.Key ResponsibilitiesPerform behavioral modeling (BM) of analog designs to enable digital verification.Conduct mixed‑signal dynamic verification (without AMS) using chip‑level digital design tools.Write, simulate, and debug Verilog/SystemVerilog verification code.Use Cadence Virtuoso Schematics to interface with analog designs.Develop test plans, verification strategies, and scalable testbench automation.Collaborate with DSP, analog, and digital engineering teams to validate high‑speed designs.Present verification results, maintain coverage metrics, and ensure first‑pass success in silicon.Minimum Qualifications5+ years of mixed‑signal verification experience.Strong background in Behavioral Modelling (BM) for analog‑to‑digital verification.Hands‑on Verilog/SystemVerilog verification coding.Familiarity with Virtuoso Schematics.Basic understanding of analog design fundamentals.Preferred QualificationsExperience with UVM (Universal Verification Methodology).Background working with both Synopsys and Cadence verification tools.Understanding of advanced verification infrastructure – simulators, waveform viewers, coverage, execution automation.Proven track record of building portable/scalable test environments.Strong communication skills; ability to write test plans, document results, present to multi‑functional teams.Seniority LevelEntry level.#J-18808-Ljbffr

    Numbers & Facts

    LocationDallas, TX

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