Optical Engineer III, PIC Design & Analysis

Optical Engineer, PIC Design & Analysis
Location: 100% Onsite at Redmond, WA
Contract Duration: 2 years
Pay Rate: $80/hr on W2
Benefits: Health, Dental, Vision, PTO, 401K


Are you passionate about pushing the boundaries of integrated photonics and advanced optical systems?
We are seeking an experienced Optical Engineer III to join a world-class R&D team developing next-generation near-to-eye display technologies. In this role, you will design, simulate, fabricate, and validate cutting-edge Photonic Integrated Circuits (PICs) that enable breakthrough performance in emerging optical platforms.

This is a highly technical position for engineers who thrive at the intersection of optical design, photonic device modeling, semiconductor fabrication, and experimental validation. You will collaborate with multidisciplinary teams of researchers, engineers, and program leaders to transform innovative concepts into manufacturable photonic solutions.
 

About the Team

The team is a highly innovative Research & Development (R&D) organization focused on advancing next-generation near-to-eye display systems through cutting-edge photonics and integrated optical technologies. Working at the intersection of optical engineering, semiconductor fabrication, and advanced display architectures, the team is responsible for developing breakthrough Photonic Integrated Circuit (PIC) solutions that enable future AR/VR and wearable computing experiences.

This multidisciplinary group brings together optical engineers, photonics researchers, device physicists, semiconductor experts, and Technical Program Managers to solve complex challenges in device performance, manufacturability, and system integration. The team operates in a fast-paced research environment where innovation, experimentation, and technical rigor are highly valued.

As a key contributor, the Optical Engineer will collaborate closely with technical leadership and cross-functional stakeholders to drive PIC design, simulation, fabrication, characterization, and tapeout activities. The role serves as a critical bridge between advanced photonics research and product development, directly influencing the future of integrated photonic technologies and next-generation display systems.

Job Responsibilities

• Design and develop complete Photonic Integrated Circuits (PICs), from
• fundamental component blocks to full-circuit implementations, with a strong emphasis on active device integration.
• Generate, verify, and prepare fabrication-ready layout files, ensuring compliance with foundry Process Design Kits (PDKs) for external fabrication.
• Conduct systematic design analysis, including optimization and parametric studies, to guide design decisions.
• Support the entire design-to-fabrication pipeline, from initial concept through tapeout, coordinating closely with cross-functional teams and external partners.
• Collaborate with program leadership, Technical Program Managers (TPMs), and researchers on PIC designs that align with overall program objectives.

• MS or Ph.D. degree in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
• 3+ years of hands-on experience in the design, simulation, and layout of PICs for visible or IR wavelengths on platforms such as Si, SiN, LiNbO, or BTO.
• 3+ years of experience utilizing photonic device simulation and electromagnetic modeling tools for both component and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).
• 2+ years of experience with PIC layout tools and GDSII generation (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including familiarity with foundry PDK integration and design rule verification.
• 2+ years of experience with scientific programming (e.g., Python or MATLAB) for scripting, design automation, and analysis.
• 1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, including an understanding of fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non-idealities).

• 3+ years experience in active PIC design, fabrication, and validation, particularly for visible wavelengths on LiNbO or BTO platforms.
• 3+ years of experience in design space exploration, sensitivity analysis, and statistical performance/yield modeling for photonic circuits.
• 3+ years of experience with one or more major photonic simulation tool suites (e.g., Lumerical, Synopsys, COMSOL, or equivalent).
• 2+ years of experience utilizing photonic circuit-level simulation tools (e.g., Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for system-level performance evaluation.
• 2+ years of experience in photonic device characterization and test, including both optical and electro-optic measurements.
• 1+ years experience with fiber optics, free-space optics, PIC packaging, and comprehensive device characterization.
• 1+ years experience with semiconductor fabrication processes and a deep understanding of process-induced performance limitations, such as optical losses, sidewall roughness, and process variability.
• Demonstrated ability to directly incorporate fabrication constraints into PIC designs (e.g., optimizing minimum feature sizes and bend radii, implementin effective tapering strategies, and using layout techniques to mitigate scattering and coupling losses).

• PIC Design & Simulation: 3+ years designing, simulating, and laying out photonic integrated circuits (PICs) for visible/IR wavelengths.
• Photonic Modeling Tools: Proficiency with tools like Lumerical, Ansys Photonics, Synopsys RSoft, or COMSOL for device/circuit analysis.
• PIC Layout & Tapeout: Experience with layout tools (KLayout, Cadence Virtuoso, gdsfactory), GDSII generation, and supporting tapeouts at commercial foundries.

• Active PIC Design & Validation: Experience in active PIC design, fabrication, and validation, especially for visible wavelengths.
• Device Characterization: Skills in optical/electro-optic measurements, fiber optics, free-space optics, and PIC packaging.
• Statistical Modeling & Sensitivity Analysis: Experience in design space exploration, yield modeling, and incorporating fabrication constraints.

Education

• Master's degree or Ph.D. in Electrical Engineering, Optical Sciences, Physics, or a closely related field.