Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.
Responsibilities:
7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
Experience:
7+ years of experience in physical design roles and related activities.
Proven ability to adhere to tight schedules and implement low-power design techniques.
Experience in System-on-Chip (SoC) design and implementation.
Skillset:
Expertise in sub-7nm node technologies.
Familiarity with industry-standard EDA tools and their capabilities.
Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.
Education:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
Additional Qualifications:
Licenses: Not required Certifications: Not required Shift Hours: 8:00AM -5:00 PM EST About US Tech Solutions: US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.
US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring. IND01
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Numbers & Facts
Location
San Jose, CA
Skills
ASIC (Application Specific Integrated Circuit)unmatched
Cadenceunmatched
Computer Engineeringunmatched
Computer Scienceunmatched
DFT (Design for Test)unmatched
Design Flowsunmatched
Electrical Engineeringunmatched
Electro-migrationunmatched
Electronic Design Automationunmatched
IR (Infrared)unmatched
Identify Issuesunmatched
Industry Standardsunmatched
Low Powerunmatched
Place and Routeunmatched
Problem Solving Skillsunmatched
RTL Designunmatched
Scripting (Scripting Languages)unmatched
System-on-a-Chip (SoC)unmatched
Tcl-Tkunmatched
Technical/Engineering Designunmatched
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