Principal DV Engineer

• Lead the DV effort of a high-end CPU project. Architect and implement testbenches and their components using UVM-based methods. Lead the effort in building in-house BFMs, unit-level testbenches and stimulus. Work with the design team to create testplans. Implement checkers/assertions/coverages. Drive directed testcases and controlled random testcases based on the testplans. Work on the core-level verification using in-house testbenches. Triage bug reports, profile failure cases, check functional coverage and drive the effort of directed testcase generation.