DEG Careers – Principal Hardware Architect & Engineering Manager Location: Irvine, CAEmployment Type: Full-timeReports To: CEO / Executive LeadershipRole Summary The Principal Hardware Architect & Engineering Manager is the senior technical and execution authority for DEG's FPGA-based hardware platforms. This role combines hands‑on hardware architecture and board‑level design with direct management of the hardware and FPGA engineering function.This position owns:Hardware system architectureHardware FPGA integrationEngineering execution, priorities, and deliveryThis is not a pure people‑management role and not a layout‑only role. It is a hands‑on technical leadership position with real accountability.Core Responsibilities System & Hardware Architecture Define system‑level hardware architecture for PCIe, FMC/FMC+, and VPX platformsArchitect high‑speed data acquisition and playback systemsSelect and qualify key technologies (FPGAs, ADCs/DACs, clocking subsystems)Define PCIe Gen4/Gen5 hardware architecture and throughput strategyEstablish hardware design standards reused across product familiesOwn technical tradeoffs involving performance, risk, cost, and scheduleBoard‑Level Hardware Design Own complete board designs from concept through production releaseDrive schematic capture for FPGA subsystems, high‑speed serial interfaces, memory, power and clockingDefine PCB stackups, routing constraints, and SI/PI requirementsWork directly with PCB designers to ensure correct implementationLead board bring‑up, debug, and validationResolve cross‑discipline hardware issues (hardware FPGA test)Define FPGA‑facing hardware architecture (JESD204 topology, clock domains, reset strategy, PCIe interfaces)Review FPGA designs for hardware compatibility and system correctnessCollaborate with FPGA engineers on interface definition and partitioningEnsure hardware supports FPGA timing, clocking, and throughput needsThis role requires architectural understanding of FPGA systems, not day‑to‑day RTL development.Directly manage hardware and FPGA engineers (employees and contractors)Own engineering priorities, schedules, and resource allocationBalance new development, sustaining engineering, and customer‑driven workLead design reviews, release decisions, and technical risk assessmentsSet expectations for design quality, documentation, and release disciplineCoordinate engineering work across hardware, FPGA, software, and testAct as the escalation point for technical and execution issuesTechnical Leadership & External Interface Serve as the final technical authority for hardware decisionsMentor engineers and enforce engineering standardsInterface with customers on deep technical topics when requiredSupport proposal development and technical responsesPreserve technical continuity across product generationsRequired Qualifications 15+ years experience in complex digital and mixed‑signal hardware designProven ownership of complete board designsDemonstrated experience leading engineering teams or technical groupsDeep expertise in PCIe, SERDES, JESD204B/C systems, clocking and power architectureWorking knowledge of FPGA architecture sufficient to guide integrationStrong bring‑up and debug experienceComfortable making final technical and execution decisionsU.S. Person (citizenship or permanent residency)Preferred Experience AMD/Xilinx UltraScale+ or Versal platformsWideband ADC/DAC or Direct RF systemsDefense or aerospace programsSmall‑team, high‑ownership environmentsCompetitive salary and comprehensive benefits package: Health insuranceDental insuranceVision insuranceRetirement plan with employer matching.Paid time offExciting projects with the potential to make a significant impact in the field of electronic design.A collaborative and inclusive team culture that values creativity, initiative, and technical excellence.Delphi Engineering Group is a military and aerospace manufacturer requiring strict adherence to ITAR requirements. As a condition of employment applicants must provide proof of US Citizenship (no green cards or visas).#J-18808-Ljbffr