Principal High-Speed Analog Circuit Design Engineer

Celero Communications
  • San Jose, California
  • $200,000–$300,000 Per Year
3 days ago

Job Description

Principal High-Speed Analog Circuit Design Engineer

About the job 
Are you an Analog Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology powering next generation AI? We are looking for an Analog Design Engineer – someone who is excited to join a fast-growing Start-Up Company growing a group of diverse individuals responsible for handling high-speed mixed-signal circuit designs! Candidate will have the opportunity to architect and design circuits for high-performance transceivers and other critical analog functions.

What You Will Do
• High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.)
• Clock generation and distribution (VCOs, PLL, clock distribution, etc.)
• Fundamental analog blocks (bandgap references, LDOs, temp sensors, etc.)
• New techniques for the development of next generation optical transceiver 
• Design of custom passive components, from concept to silicon implementation
• Supervise analog layouts within advanced process nodes
• System verification and circuit design spec creation
• Silicon bring-up, debug and support
• Team communication and documentation 

What You Will Bring
• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of experience
• Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE, and post layout extraction tools) is a must
• Experience in advance CMOS design and verification flows (tools to evaluate self-heating, electromigration, safe operating area)
• Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other) is a plus
• Knowledge of the fundamentals on electromagnetism, lump models, and high frequency design
• Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus
• Strong communication and documentation skills 

Annual Base Salary Range: $200,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
 

Numbers & Facts

LocationSan Jose, California
Salary$200,000–$300,000 Per Year
Websitehttps://celero.inc

Skills

  • Analog Circuit Designunmatched
  • Artificial Intelligence (AI)unmatched
  • Broadbandunmatched
  • CMOSunmatched
  • Circuit Designunmatched
  • Communication Skillsunmatched
  • Debugging Skillsunmatched
  • Design Flowsunmatched
  • Design Verificationunmatched
  • Develop Methodologiesunmatched
  • Documentationunmatched
  • Electrical Engineeringunmatched
  • Electro-migrationunmatched
  • Electromagnetic Modelingunmatched
  • Electromagnetismunmatched
  • HFSS (High Frequency Structure Simulator)unmatched
  • Mixed Signal Circuitsunmatched
  • Mixed Signal IC Designunmatched
  • Optical Transceiversunmatched
  • PLL (Phase-Locked Loop)unmatched
  • Power Amplifierunmatched
  • Requirements Managementunmatched
  • Silicon Bringupunmatched
  • Simulationunmatched
  • Startupunmatched
  • Technical/Engineering Designunmatched
  • Transceiversunmatched

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