CAD/CAM (Computer-Aided Design/Computer-Aided Manufacturing), Centers for Disease Control and Prevention (CDC), Cloud Computing, Code Coverage, Communication Skills, Cross-Functional, DDR2 (Double Data Rate Two SDRAM), DFT (Design for Test), Debugging Skills, Digital Circuits, Double Data Rate SDRAM, EEPROM, Electronic Design Automation, Embedded Systems, Financial Control, Graphic Design, High Reliability, I2C, Industry Standards, Integrated Circuit (IC) Design, Integrated Circuits (ICs), Joint Electron Device Engineering Council (JEDEC), Linux Operating System, Logic Design, Low Power, Memory Hardware, Mentoring, Microcontroller, Mixed Signal Circuits, Needs Assessment, Network Operations Center, Perl Programming Language, Power Management, Product Design, Python Programming/Scripting Language, Requirements Management, Scripting (Scripting Languages), Semiconductors, Simulation, SystemVerilog, Tcl-Tk, Team Lead/Manager, Team Player, Technical/Engineering Design, Thermal Sensor, Verilog Hardware Description Language
Theme Debug: Theme Hook views_view_fields
BEGIN OUTPUT from coremodulesviewstemplatesviews-view-fields.html.twig
Theme Debug: Theme Hook views_view_field
Job Responsibility
Montage Technology has opened a new U.S. location in the Johns Creek GA area offering a hybrid work environment. We are a leading semiconductor company specializing in datacenter enterprise infrastructure and memory interface products. There will be many hands-on learning experiences with significant program ownership and career growth.
Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance low-power IC solutions for cloud computing and data center markets. Montage Technology provides industry-leading DDR2 to DDR5 memory interface products for the demanding cloud computing and data center markets. Our robust product portfolio includes the critical components required by the memory modules such as a Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM, Hub SPD, Hub Temperature Sensor (TS), and Power Management IC (PMIC).
Compliant with JEDEC specifications, these products are designed for a variety of memory modules such as RDIMM, LRDIMM, NVDIMM, UDIMM, SODIMM, MRDIMM, etc., to enable high-speed, large-capacity, high-reliability, and low-power memory solutions for high-performance computing.
We are looking for a Principal level Digital Design Engineer
We are seeking a Principal level Digital Design Engineer with over 15 years of experience who will help architect and develop RTL for various products with the area of focus being DDR server-class memory controllers. The ideal candidate will have RTL to GDSII flow experience using industry-standard tools. In addition, knowledge of embedded micro-controllers such as RISCV and I2C/I3C protocols are advantageous.
Responsibilities
Your contribution would be to work with other global team members in designing both building blocks for the various products as well as designing the entire new product for the company.
- Mentor and lead cross-functional teams to architect, develop, and debug digital and mixed-signal circuits
- Design various logic & state machines in SystemVerilog
- Develop and debug RTL using industry-standard simulation and synthesis tools along with LEC, CDC, Lint, DFT, and STA tools
- Provide PPA (Power Performance Area) and schedule estimates as well as design specifications for the RTL
- Coordinate with Verification AMS design teams to ensure proper operation and functional and code coverage
- Provide floor-planning and support integration of digital & analog circuits at top level
- Work in cooperation with the methodology and CAD teams
- Coordinate with other stakeholders in identifying needs and improvements
Job Qualification
Must have:
- 15 years of industry experience
- Experience and deep understanding in the architecture definition of DDR4/5 server-class memory controllers
- Understand how to obtain minimum latency and maximum bandwidth
- Understand the tradeoff with command placement and scheduling to efficiently manage activate and pre-charge commands
- Familiarity with ECC, SECDEC, and CRK
- Knowledge of CHIAXI interconnect and bus protocols
- Knowledge of JEDEC memory standards
- Experience in high-speed and low-power digital design in advanced deep sub-micron processes
- Proficient with SystemVerilog and Verilog RTL for both behavioral simulations and synthesis
- Proficient with Design Compiler and PrimeTime
- Programming scripting know-how (e.g., Perl, Tcl, and/or Python)
- Experience with Linux
- Good communication skills and ability to take ownership
- Experience with embedded micro-controllers is beneficial
M
Montage Technology Co Ltd