Principal PLL Design Engineer

Celero Communications
  • San Jose, California
    3 days ago

    Job Description

    Principal PLL Design Engineer

    About the job 
    Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.

    What You Will Do
    • Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range 
    • Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre 
    • Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization 
    • Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies 
    • Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment 
    • Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies 

    What You Will Bring
    • Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience. 
    • Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)  
    • Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs 
    • Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling 
    • Strong communication and documentation skills 

    Annual Base Salary Range: $2000,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
     

    Numbers & Facts

    LocationSan Jose, California
    Websitehttps://celero.inc

    Skills

    • Analog Circuit Designunmatched
    • Analog/Digital Converterunmatched
    • Artificial Intelligence (AI)unmatched
    • CMOSunmatched
    • Cadenceunmatched
    • Communication Skillsunmatched
    • Digital/Analog Converterunmatched
    • Documentationunmatched
    • Electrical Engineeringunmatched
    • Electro-migrationunmatched
    • Electromagnetismunmatched
    • Floorplanningunmatched
    • HFSS (High Frequency Structure Simulator)unmatched
    • Laboratory Equipmentunmatched
    • MATLABunmatched
    • Optical Transceiversunmatched
    • Oscillatorunmatched
    • PLL (Phase-Locked Loop)unmatched
    • Phase Noise Analysisunmatched
    • Power Generationunmatched
    • Pumpsunmatched
    • SERDESunmatched
    • Startupunmatched
    • Technical/Engineering Designunmatched
    • Topologyunmatched
    • Transceiversunmatched

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