Principal Quantum Design Verification Engineer

At Microsoft Quantum, we aim to empower science and scientists to solve the worlds biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence, and quantum information technology. Our team is dedicated to developing the first scalable, fault-tolerant quantum computer and is leading progress in areas ranging from quantum hardware and error correction to comprehensive integration with Azure. Our full-stack strategy spans the physics of quantum devices through scalable readout and control infrastructures powered by cryo-electronics. We are entering a pivotal phase of accelerated growth in quantum computing, and this position presents a unique opportunity to contribute meaningfully to a transformative technology.

As a Principal Quantum Design Verification Engineer on the Quantum 1st Party Hardware System-on-Chip (SoC) team, you will play a critical leadership role in advancing the development of the teams quantum SoC verification infrastructure. Your responsibilities will include defining pre-silicon Simulation plans and post-silicon Validation/Characterization plans for SoC and Intellectual Property (IP) blocks, and coordinating individuals, contingent staff, and external vendors to deliver a high-quality design.

You will work across SoC architecture, quantum hardware, analog design, and physical design teams throughout the program lifecycle to bring SoC and IP into production at the quality required for scalable quantum systems. If you thrive on complex challenges and foundational technologies that redefine whats possible, we invite you to help shape the future of quantum computing.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. 

Responsibilities

• Own verification environments and tests for IP and SoC designs, and validate designs in simulation with both pre- and post-layout Register-Transfer Level (RTL) and netlists.
• Coordinate the execution of contingent staff and external vendors to ensure verification deliverables meet specification and schedule.
• Set up and manage databases and flows for SoC and IP repositories; set up bug-tracking systems and log, track, manage, and close bugs and issues; drive milestone reviews and status reports.
• Create test plans for pre-silicon simulation verification across both digital and analog components, including the development of Analog Mixed-Signal (AMS) simulation models.
• Collaborate with the Design For Test (DFT) team to test DFT features.
• Align verification methodologies with wider teams and drive continuous improvement to Design Verification processes for at-scale execution.
• Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams.
• Other
  • Embody our culture and values .

Qualifications

Required/minimum qualifications

• Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
  • OR Masters Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR Bachelors Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
  • OR equivalent experience. 

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:  
  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. 
  • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. § 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

• Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation).
• Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through hardware development.

Preferred qualifications

• 10+ years of design verification experience, including verification of complex SoC or large IP blocks delivered to production.
• 5+ years of experience coordinating verification across large SoC or IP programs, including establishing verification flows and methodology.
• Hands-on expertise with Universal Verification Methodology (UVM), Open Verification Methodology (OVM), and SystemVerilog.
• Experience building testbenches, generating stimulus, creating simulation environments, and debugging complex designs.
• Experience with Analog Mixed-Signal (AMS) verification across the design lifecycle, including analog and digital interface verification, AMS modeling and simulation, and silicon characterization through release to production.
• Proficiency in MATLAB for complex modeling and visualization.
• Proficiency in a scripting language such as Python, Ruby, or Perl, including automation of simulation and data analysis.
• Experience writing tests in C and C++.
• Background verifying complex chips such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), AI accelerators, or networking SoCs.

Quantum Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.