Principal Silicon Design Subsystem Lead

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsofts over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. 

As Microsofts cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for an engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.  

We are looking for a Principal Silicon Design Subsystem Lead to join the team. 

Responsibilities

• Deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property (IP) and System on Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner.  
• Technically lead one or more Subsystems.  
• Oversee development of custom Subsystem (SS) components with focus on architectural and micro-architectural based functions and features. 
• Interact with architects to develop micro-architectural specifications and work with DV engineers to execute them. 
• Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP- or SS-level verification. 
• Write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness. 
• Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments. 
• Collaborate across teams on vertical and horizontal reuse of components. 
• Define and implement functional coverage and drive coverage closure. 
• Write makefiles and scripts for infrastructure. 
• Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. 
• Provide technical leadership through mentorship and teamwork. 

Qualifications

Required/minimum qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Other Requirements 

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. 
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.  

Additional or Preferred Qualifications 

• 12+ years of relevant experience 
• 5+ years experience with lead roles across cross-functional / cross-time-zone engineering teams. 
• Lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar 
• Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs  
• Experience in Scripting language such as Python or Perl 
• Hands on experience in Formal property verification  
• Experience with verification for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM) 
• Experience debugging Register Transfer Level (RTL) designs as well as simulation and/or emulation environments. 
• Experience with design quality and static checks, DFT implementation and hand off to physical design. 

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.