Principal SOC Modeling Architect

Overview

Join Microsoft Azures Firmware Center of Excellence to define the future of pre-silicon software development for Microsoft custom silicon. This Principal Modeling Architect is a cross-program technical leader who solves hard system-level problems, establishes scalable architecture and engineering patterns, and then transitions execution ownership to development teams and junior engineers for long-term delivery.

As Principal SOC Modeling Architect, you will provide technical leadership across multiple Azure silicon programs. You will drive the architecture and evolution of high-fidelity virtual platforms that enable firmware, operating system, platform development, validation, and silicon bring-up before hardware is available. This is not a single-project implementation role. The expectation is to work across projects, identify and solve the hardest technical problems, prototype and de-risk solutions, establish direction, and then hand off durable execution paths to the broader engineering team.

Responsibilities

Why This Role Is Unique

• Develop firmware and software before hardware exists.
• Influence silicon architecture and platform strategy across Azure hardware programs.
• Solve the organization s hardest modeling, firmware, bring-up, and system integration problems.
• Work across multiple programs as a trusted technical leader rather than owning only one execution lane.
• Shape Microsoft s future virtual platform and hybrid development strategy.
• Build reusable solutions that enable firmware, validation, architecture, and platform teams to move faster.

Technical Leadership and Strategy

• Lead resolution of complex system-level challenges spanning virtual platforms, firmware, silicon architecture, validation infrastructure, software enablement, and hybrid execution environments.
• Define architectural direction for SystemC/TLM-based virtual platforms supporting multiple generations of Azure silicon.
• Identify technical risks, technology gaps, and scaling challenges across programs, then drive practical solutions that can be adopted by multiple teams.
• Establish engineering standards, modeling practices, reusable frameworks, debug strategies, and validation approaches that improve quality and reduce duplicated effort.

Cross-Program Architecture and Influence

• Work across multiple silicon programs as a shared technical leader and subject matter expert.
• Define reusable platform capabilities across Azure hardware initiatives rather than creating one-off project-specific implementations.
• Influence silicon architecture, firmware readiness, validation methodologies, and platform bring-up strategy through early technical engagement.
• Drive alignment across architecture, design verification, firmware, operating system, emulation, prototyping, and platform teams without relying on direct authority.

Modeling and Firmware Enablement

• Design and develop SystemC/TLM-2.0 models for complex SoC subsystems including PCIe, memory, boot infrastructure, compute clusters, interconnect, and platform services.
• Develop and debug low-level firmware and validation software running on virtual platforms.
• Support firmware bring-up activities including UEFI, Windows Boot, PCIe initialization, platform enumeration, early driver enablement, and operating system integration.
• Debug complex interactions spanning hardware, firmware, operating systems, virtualization environments, simulation infrastructure, host systems, and modeling frameworks.
• Analyze and optimize simulation performance, scalability, usability, and debug productivity across large SoC and multi-SoC environments.

Hybrid Platform Strategy

• Contribute to architectural integration of virtual platforms with emulation and prototyping systems including ZeBu, HAPS, Helium, Palladium, and Protium.
• Help define Microsoft s long-term hybrid development strategy by combining simulation, emulation, and prototyping technologies to scale pre-silicon software development and validation capacity.
• Partner with DV, firmware, architecture, and platform teams to determine where virtual models, emulation, FPGA prototyping, and hybrid flows provide the most value.

Mentorship and Organizational Scale

• Mentor engineers through design reviews, architecture guidance, technical coaching, and hands-on problem solving.
• Prototype, prove, and de-risk complex solutions before transitioning ownership to development teams for long-term execution.
• Build organizational capability by enabling junior and senior engineers to understand, maintain, and extend solutions after initial architecture direction is established.
• Raise engineering quality by promoting reusable, maintainable, scalable solutions rather than short-term fixes.

Qualifications

Minimum Qualifiations:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
• OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
• OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
• OR equivalent experience.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:

• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years technical engineering experience with coding,

• OR Master s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years technical engineering experience with coding,

• OR Bachelor s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 12+ years technical engineering experience with coding,

• OR equivalent experience.

• 3+ years experience leading technical projects beginning-to-end.

• Experience with SystemC and TLM-2.0 modeling.

• Experience with Synopsys Virtualizer, Arm Fast Models, Cadence Helium, or similar virtual platform technologies.

• Experience developing or debugging firmware, bootloaders, device drivers, platform software, PCIe firmware, UEFI, Windows Boot, Linux Boot, or silicon bring-up activities.

• Experience with SoC architecture, interconnects, IP integration, PCIe, USB, memory subsystems, boot flows, or platform services.

• Experience optimizing simulation performance, scalability, and debug productivity in simulation or system environments.

• Experience with hybrid, emulation, or prototyping environments including ZeBu, HAPS, Palladium, Protium, or similar platforms.

• Experience defining reusable platform architecture, modeling frameworks, reusable IP libraries, or engineering standards across multiple programs.

• Demonstrated ability to solve ambiguous, high-impact technical problems and influence technical direction across organizations without direct authority.

• Strong intuition for hardware/software interactions, system performance bottlenecks, and practical engineering tradeoffs.

• Passion for mentoring engineers, transferring knowledge, and building organizational capability beyond a single project.

• Experience developing complex software systems using C/C++.

• Experience in firmware, systems software, silicon development, virtual platforms, or pre-silicon development environments.

• Experience working across hardware, firmware, and software boundaries.

• Experience leading technical projects from architecture through delivery.

• Strong debugging, root-cause analysis, and technical problem-solving skills.

Firmware Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.