Principal Verification Engineer

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

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Job Description:

About the Role

SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for the CPU Core Load-Store Unit in a high-performance out-of-order core.

This is a principal tech-lead role for an engineer who can define architecture-aware verification strategy, identify the highest-risk microarchitectural issues early, and solve the most difficult LSU verification problems spanning load/store ordering, hazard handling, cache coherency, and memory consistency.

The role requires close partnership with architecture, RTL, formal, performance, and verification teams to ensure design intent is captured correctly, debugability is considered early, and signoff quality is achieved with scalable methodology and strong technical judgment.

Responsibilities

• Lead verification strategy for the CPU Core LSU, including block-level and core-level planning, execution, debug, coverage analysis, and closure.
• Define verification strategies for complex LSU behaviors including load/store ordering, dependency handling, hazard detection, barrier and fence behavior, memory consistency, atomics, and interaction with weak memory ordering rules.
• Drive verification of cache-facing LSU behavior including cache hit and miss handling, snoops, evictions, coherency state interactions, and data correctness across L1 and downstream memory hierarchy interactions.
• Own verification of corner cases involving overlapping accesses, false sharing, outstanding loads and stores to the same cache line, data forwarding, speculative execution repair, and out-of-order response handling.
• Develop high-value checkers, scoreboards, assertions, stimulus strategies, and coverage models that expose corner cases and improve bug-finding efficiency for coherency and consistency scenarios.
• Apply the right verification method for the problem, including simulation, formal techniques, and emulation, to improve quality, accelerate turnaround, and strengthen debug efficiency on large CPU verification workloads.
• Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification quality before implementation hardens.
• Drive efficient root-cause analysis across specification, RTL, test content, assertions, and verification infrastructure, especially for difficult coherency and memory-ordering failures.
• Mentor engineers across the organization, influence methodology, and shape reusable verification approaches that benefit future generations of CPU cores and memory subsystems.

Minimum Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification, with depth appropriate for a Principal / T6 role.
• Direct experience with out-of-order core verification and strong understanding of CPU microarchitecture.
• Deep expertise in Load-Store Unit verification, memory ordering and consistency, or closely related CPU core microarchitecture areas.
• Strong understanding of cache-coherent systems, memory hierarchy behavior, and verification of ordering, snooping, and flow-control semantics across the memory subsystem.
• Strong knowledge of verification methodology including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
• Strong software development, scripting, and automation skills for building scalable verification infrastructure and workflows.

Preferred Qualifications

• Direct experience verifying cache coherency, weak memory ordering, and multicore memory-consistency challenges.
• Experience with formal verification of LSU or memory-subsystem properties such as load data correctness, store ordering, barrier synchronization, dependency handling, liveness, and forward progress.
• Experience verifying interactions across LSU, cache hierarchy, coherent interconnect, and memory subsystem boundaries in large SoCs.
• Experience with litmus-style or memory-model-oriented verification approaches for exposing deep coherency and consistency bugs.
• Experience collaborating effectively with performance, compiler, software, formal, and system verification teams to close verification gaps from multiple perspectives.
• Demonstrated technical leadership through mentoring engineers, influencing methodology, and driving cross-team execution on complex verification efforts.

What Success Looks Like

• Verification plans capture the real architectural and microarchitectural LSU risks early and completely.
• Difficult LSU bugs involving coherency, ordering, consistency, and cache-permission corner cases are found early, debugged efficiently, and closed with durable fixes.
• Verification quality improves across the broader CPU DV organization through stronger methodology, better technical guidance, and reusable infrastructure.
• Architecture, design, and DV teams rely on this engineer as a technical leader for the most complex LSU and memory-subsystem verification challenges in high-performance CPU development.

Working on solving verification challenges of memory management units that are being reused across several different generations of the Cores, as well as IO memory management unit. This includes hypervisor, virtualization, and guest virtualization.

BS/MS/Ph.D in EE, CE or CS

12+ years relevant experience with Core/CPU functional verification

8+ years direct experience on memory management verification

Deep understand of computer architecture

Seasoned developer using object oriented programing principles

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in

United States of America

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.