RF/Microelectronics Packaging Engineer

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.

The Packaging Engineer position requires handling all aspects of packaging development. This means planning, crafting, and developing advanced or novel packaging. The role also involves managing packaging efforts related to radio frequency communication devices.   The products range from IC’s, System In Packages, sub-assemblies, and modules. The packaging development process includes package definition, stack-up, substrate layout, bond diagram, drawings, predictive modeling combined with system testing, technical risk/cost assessment, materials and process characterization, compilation of formal documentation, collaborating with sub-contractors and internal assembly and reliability resources, and final release of product.  

Job responsibilities include but not limited to:

• Working closely with project development teams and product groups (RFIC, MMIC, Module) to develop the next generation/sophisticated/novel packaging solution for RF communication products
• Define packages and materials that meet product requirements for reliability, performance, manufacturability, and cost.
• Ensure all packaging work is completed for New Product and New Technology Introductions  
  
  • Develop and manage packaging documentation including SOWs, package drawings, and process flows
  • Build and layout of semiconductor packages including QFN, SiP, WL-CSP, RDL, Flip Chip, FO-WLP and Interposers  
• Ensure early success in package development with modeling and simulation for thermal, mechanical, and electrical
• Technically oversee vendors in the manufacture of said packages in conjunction with manufacturing engineers
• apply your assembly knowledge of die attach, Wirebond, bumping, overmolding to advise product groups on options available to solve problems  
• identify suitable IC, sub-assembly, and module package options and perform feasibility studies for new products
• interact with product groups for package/cost optimization along with mechanical engineering
• specify and conduct reliability testing by vendors to insure the reliability of the packaged product 
• Coordinate package related activities across multiple organizations including Marketing, Design, Applications, Test, Assembly Engineering, Quality, and Manufacturing (internal and external factories)
• Address and solve materials and processing issues that may occur during the development process
• Manage the package process using industry standard project management tools.
• Develop and maintain the packaging and technology roadmap through proposal support and long term technology programs

• 10+ years in semiconductor packaging including experience in package assembly process, package engineering, quality & reliability and the intersection/relationship of packaging to test.
• Bachelor's Degree in Electrical, Mechanical, Materials Engineering or related technical discipline
• Deep understanding of micro-electronic package structure, mechanical, electrical and thermal performance.
• Solid grasp of heat transfer and its relation to material properties  
• Packaging knowledge in RFIC, millimeterware, System In Package, sub-assembly, and/or modules.
• Experience in semiconductor package design with demonstrated experience in one or more of the following:  QFN, SiP, BGA, WL-CSP, Flip Chip and Bumping or FO-WLP
• Strong understanding of Die Prep, Assembly (die attach, Wirebond, flip chip, etc) and Surface Mount Technology (SMT) process-equipment is desired.
• Have a high tolerance for ambiguity and solid interpersonal skills
• In-depth knowledge of interconnect reliability daisy chain testing, CPI and BLR.      
• Understands the metallization schemes for laminates, interposers and SMT.
• Knowledge of statistical methods and Building of Experiments  
• Must be able to work autonomously and help determine methods and procedures. 
• Customer service oriented.
• Ability to work with build teams to translate IC/system requirements input packaging configurations  
• Ability to manage and drive packaging
• US Government position. US Citizenship required
• Ability to travel up to 10%
  
  This is an onsite role based in Tempe, AZ
  
  #LI-BBS

• Strong Preference for RF, Microwave or mmWave experience
• Experience with package build software like Cadence APD/SiP  
• Experience with electronic compose and layout tools such as Cadence Concept HDL, Mentor Graphics DxDesigner, or Zuken  
• Prior volume OSAT experience is highly desired
• Experience in ITAR and Mil programs
• SolidWorks tool usage
• Knowledge or exposure of wafer to wafer bonding
• Knowledgeable about ATE 
• IMAPs and/or MEPTEC membership
• Knows the latest semiconductor packaging trends.  
• Understands MIL-STD-883 and JEDEC requirements.
• Proficient user of Microsoft Excel and other Office products.

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click

careers@viasat.com