RTL Engineer, Networking ASIC
Full Time opportunity in Saratoga, CA
We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASIC’s. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking chips.
Responsibilities
Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC’s, focusing on latency optimization and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling / arbitration design.
Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Work with verification team to conduct thorough testing and validation to ensure functionality and reliability.
Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols, and high speed interconnects such as UCIe.
Qualifications
ME/BE with a minimum of 8-15 years of experience.
Hands-on knowledge of SystemVerilog and Verilog is mandatory.
Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
Proven expertise in designing and optimizing scheduling and QoS mechanisms.
Experience with Ethernet and IP protocols.