Senior ASIC/SoC RTL Design Engineer: IP & Tape-Out Lead

AMD

San Jose, CA

JOB DETAILS
SKILLS
ASIC (Application Specific Integrated Circuit), ASIC Design, Embedded Systems, IP (Internet Protocol), Intrusion Prevention Systems, Maintain Compliance, Mentoring, RTL Design, Semiconductors, System-on-a-Chip (SoC), Technical/Engineering Design, Verilog Hardware Description Language
LOCATION
San Jose, CA
POSTED
Today

A leading semiconductor company in San Jose is seeking a Senior ASIC Design Engineer to design and develop cutting-edge IPs for embedded products. You will oversee the RTL design lifecycle, ensuring compliance with performance and timing requirements, while mentoring junior engineers. The ideal candidate has expertise in Verilog coding and a robust understanding of the ASIC design flow, with multiple tape-outs. This role promotes innovation and collaboration within a dynamic team environment.#J-18808-Ljbffr

About the Company

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AMD