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Skills
Analysis Skillsunmatched
Apacheunmatched
Artificial Intelligence (AI)unmatched
CPU (Central Processing Unit)unmatched
Cloud Computingunmatched
Dynamic Analysisunmatched
Fablessunmatched
IR (Infrared)unmatched
Leading Edge Technologyunmatched
Network Operations Centerunmatched
Network Performance/Analysisunmatched
Power Engineeringunmatched
Silicon Bringupunmatched
Simulationunmatched
Smart Homesunmatched
Smartphonesunmatched
Wi-Fiunmatched
Description
MediaTek is a global fabless semiconductor industry leader, providing solutions from the edge to the cloud and powering over 2 billion connected devices every year. Established in 1997, our leading-edge technologies keep the world connected and enhance everyday life. At the forefront of innovation, MediaTek drives advancements in transformative technologies such as AI, 5G/6G, and Wi-Fi 8. Our high-performance, power-efficient solutions form the foundation for a smarter, more connected world, enabling devices from smartphones, smart homes, and AI PCs to high-performance computing, automotive, and AI data centers. As a trusted partner to the world's leading brands, we are committed to ensuring access to world-class technology for everyone. Our dedication to accelerating AI underscores our mission to enrich the future of humanity.
About the Role
We are looking for a Senior CPU Power Delivery Engineer to join our CPU subsystem team. You will own the end-to-end power delivery architecture for high-performance mobile and compute SoCs - from PDN design and analysis through silicon bring-up and characterization.
Responsibilities
Design and analyze power delivery networks (PDN) for CPU clusters (including big/mid/little core configurations) across advanced process nodes (5nm, 4nm, 3nm)
Develop PDN impedance models and perform frequency-domain and time-domain simulations to meet target noise margins
Define power grid architecture, decap strategy, and bump/pin assignment in collaboration with package and board teams
Perform IR drop and dynamic voltage droop analysis using tools such as Apache Redhawk, Voltus, or equivalent
Work closely with CPU microarchitecture and physical design teams to optimize power gating, DVFS operating points, and voltage domains
Characterize silicon power behavior during bring-up; correlate simulation results with measured data
Define and drive power delivery specifications for package, board, and PMIC/VR selection
Contribute to design rule development and sign-off criteria for power integrity