Senior Design Engineer for Low Latency Networks
The role is for an FTC New Hire in Alpharetta providing designs for major strategic initiatives within ENS, the role will specifically focus on SETI related projects within the North America region whilst providing backup for SETI initiatives in other regions i.e. EMEA & Asia. SETI programs require an intimate working knowledge of low latency network design, precision timing for both FINRA and MifiD II regulatory compliance, exchange connectivity, multicast routing and market data distribution, dynamic routing (OSPF & BGP), QoS, Matrix switching and network instrumentation.
The role requires the incumbent to provide Level 4 Engineering support for major operational incidents on a follow the sun basis as well as providing SME guidance for peers. The role holder is also expected to provide thought leadership on emerging technologies and architectures. The current low-latency infrastructure Design Engineering SME who has resigned was responsible for a number of low latency and exchange connectivity technologies and the workload cannot be redistributed to other team members. All other team members have equally critical workloads and cannot easily absorb the additional load.
CCIE and intimate working knowledge of low latency network design, precision timing (ntp & ptp), exchange connectivity, multicast routing and market data distribution, dynamic routing (OSPF & BGP), QoS, Matrix switching and network instrumentation- taps, SPAN, netflow, sFlow etcNAT, MPLS, IPSec, A10/F5 load-balancer, Arista, Cisco, Metameko, Exablaze, Corvil, FSM Labs and Spectracom timing products. Familiarity with merchant/vendor silicon low latency product. Virtualization, MPLS and security best practices. 40G/100G ethernet and wireless low latency (for e.g. microwave networks). Knowledge of Ansible and Python programming a plus.