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Senior Design Verification Engineer Memory Controller Subsystem (HBM)

Calsoft Labs

San Jose, CA

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JOB DETAILS
SKILLS
Code Coverage, Debugging Skills, Design Verification, Financial Control, Memory Hardware, Memory Subsystem, Perl Programming Language, Power Management, Python Programming/Scripting Language, QoS (Quality of Service), RTL Design, Scripting (Scripting Languages), SystemVerilog, Systems Engineering, Technical/Engineering Design, Test Case, Unix Shell Programming, Validation Testing, Verification Engineering, Verification Plans
LOCATION
San Jose, CA
POSTED
3 days ago
Experience: 5 12+ Years

Responsibilities
  • Verify the HBM-based Memory Controller subsystem using SystemVerilog/UVM.
  • Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
  • Verify the HBM protocol, memory transactions, scheduling, ECC, QoS, power management, and performance.
  • Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
  • Collaborate with Architecture, RTL, and Validation teams through verification signoff.
Required Skills
  • Strong SystemVerilog/UVM expertise.
  • Experience verifying DDR/HBM memory controllers or memory subsystems.
  • Good understanding of HBM/DDR protocols, AXI interfaces, and memory architecture.
  • Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
  • Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).

About the Company

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Calsoft Labs

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