Senior Designer Engineer

DP Professionals
  • El Segundo, CA
  • Remote
  • Instant Apply
1 day ago

Job Description

DPP is seeking a Senior Designer Engineer for an opportunity with our client in the Aerospace industry.
 
Work Location: Fully remote
Duration: 8 months
Terms: W2 Contract
 
Responsibilities:
  • Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog).
  • Develop verification methodologies and test benches for block and system-level verification.
  • Create and execute test plans, develop test harnesses, and implement coverage models.
  • Conduct timing analysis, noise analysis, and other signoff checks.
  • Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering.
  • Support lab integration and troubleshooting activities.
  • Resolve design issues and drive solutions for timing, congestion, and other implementation challenges.
Required Qualifications:
  • 7+ years of experience in ASIC design and implementation.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
  • Experience with FPGA & ASIC design.
  • Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog).
  • Experience with Linux development environment.
  • Experience with design verification and test bench development.
Preferred Qualifications:
  • Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field.
  • Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test).
  • Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs.
  • Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM).
  • Strong object-oriented programming and scripting skills (Python, TCL, Perl).
  • Experience with physical design flows and industry-standard EDA tools.
  • Experience with RTL2GDSII physical design and signoff flows.
  • Knowledge of deep sub-micron FinFET and CMOS technologies.
  • Experience with DFT/Scan/MBIST/LBIST methodologies.
  • Experience mentoring junior engineers.
Authorized US Worker - US Citizens and those authorized to work in the US are encouraged to apply. We are unable to sponsor at this time.
 
Interested? Learn more:
Click the apply button to learn more about this position (#26-01280).
 DP Professionals (DPP) offers a range of compensation and benefits packages to our employees and their eligible dependents. DPP is a certified Woman-owned Small Business Enterprise (WBE and WOSB) with more than 25 years in the staffing industry. EOE/AA/V/D

Numbers & Facts

LocationEl Segundo, CA (
Remote
)

Skills

  • ASIC (Application Specific Integrated Circuit)unmatched
  • ASIC Designunmatched
  • Aerospace and Defenseunmatched
  • Analog/Digital Converterunmatched
  • Architectural Designunmatched
  • CMOSunmatched
  • Communication Systemsunmatched
  • Computer Engineeringunmatched
  • Computer Firmwareunmatched
  • Cross-Functionalunmatched
  • DFT (Design for Test)unmatched
  • Design Flowsunmatched
  • Design Verificationunmatched
  • Develop Methodologiesunmatched
  • Digital Signal Processing (DSP)unmatched
  • Digital/Analog Converterunmatched
  • Electrical Engineeringunmatched
  • FPGAunmatched
  • FPGA Designunmatched
  • Hardware Description Languageunmatched
  • Identify Issuesunmatched
  • Industry Standardsunmatched
  • Integration Testingunmatched
  • Linux Operating Systemunmatched
  • Mentoringunmatched
  • Noise Analysisunmatched
  • Object Oriented Programming (OOP)unmatched
  • Perl Programming Languageunmatched
  • Problem Solving Skillsunmatched
  • Product Engineeringunmatched
  • Python Programming/Scripting Languageunmatched
  • Scripting (Scripting Languages)unmatched
  • Simulationunmatched
  • SystemVerilogunmatched
  • Tcl-Tkunmatched
  • Technical/Engineering Designunmatched
  • Test Benchunmatched
  • Test Harnessunmatched
  • Test Plan/Scheduleunmatched
  • Testingunmatched
  • Timing Verificationunmatched
  • VHDL Hardware Description Languageunmatched
  • Validation Testingunmatched
  • Verilog Hardware Description Languageunmatched

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