Leads a team oflithographydevelopment engineers to drive technology development and enablementacross the full range of patterning modules for advanced CMOS technologies.
Willbe responsible fordevelopment and drivingmanufacturability across key lithography tools includingbut not limited to DUVand EUV.
Primary responsibilities willresideat the intersection of technology developmentandhigh volumemanufacturingespecially on new lithography processesthat require engineering to meet high volume requirements.
This includes driving safety,quality, performance, throughput, capability (patternfidelity),uniformityand cost.
This organization will engage closely with lithography teams in technology development as well as thehigh volumelithography teams in the factoriesand will bepart of the Manufacturing Development team.
This leader will set the goals for the team, manage the program deliverables andcoachand develop the engineers while also developing an understanding of the future needs of the organization and putting in place an organizational strategy to meet the needs of Intelfoundrytechnologiesroadmap.
The leader will be alithographysubject matter expert and have experience working with Integration and othermodules leaders such as etch and thin films to deliver modular solutionsthat meet the technology targets.
Minimum qualifications arerequiredto be initially considered for this position. Preferred qualifications are in addition to theminimumrequirements and are considered a plus factor inidentifyingtop candidates.
Minimum Qualifications:
14 years of relevant work experience in the semiconductor spacewith a strong focus on lithography.
MastersDegree in Electrical Engineering or Technical Equivalent
Prior senior management with large, multi-national manufacturing employers, preferably in high technology/scientific/semiconductor sectors with prior specialization in technology development.
Strong history of industry experience in process development, leadership, and semiconductorprocess.
Background working with a combination of investors and third- party suppliers on solution optimization/customization to meet their manufacturing needsespecially with the industry leaders in lithography solutionssuch as ASML and KT.
Engineering group leader background at global scale including leading significant factory ramp-up and process technology development in high volume manufacturing environments.
Extensive experience infabstart-up with technicaltrack recordin multiple areas of semi-conductor sector in areas such as manufacturing engineering, quality and reliability, research and development, sourcing/supply chain innovations etc.
Preferred Qualifications
Substantial technical background inlithography as used in advanced CMOS technologieswith a body of research and patents.Demonstrated history of delivering customized solutions in Research and Development and HVM organizations.Previousrelated work experience in a semiconductor foundry preferred.Requirements listed would be obtained through a combination of industry relevant job experience, internshipexperiencesandorschoolwork/classes/research.
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US: $248,400.00-350,690.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.