Senior Hardware Engineer - Micro-Architect

Quadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and hardware is targeted to run neural network (NN) inference workloads in a wide variety of edge and endpoint devices, ranging from battery operated smart-sensor systems to high-performance automotive or autonomous vehicle systems. Unlike other NPUs or neural network accelerators in the industry today that can only accelerate a portion of a machine learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code.

Role:

This is a rare opportunity to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle.

Our preference is for a candidate located in the California Bay Area who can regularly collaborate from our Burlingame office.

From time to time, the team and company gather for onsite meetings and offsite events. These in-person moments are an important part of how we build relationships, collaborate effectively, and align on priorities, and participation is expected for all team members.

• Contribute to the definition of the processor architecture by understanding its applications
• Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog
• Own Power, Performance & Area (PPA) optimization
• Contribute to timing closure through full product cycle (front end, back-end, tapeout)