Senior Layout Extraction Engineer

Overview

PDF is seeking an experienced Layout (FIRE) Extraction Engineer to join the DFI team, who is responsible for Apps Support. The Layout (FIRE) Extraction Engineer is an organized and highly motivated team player with strong initiative and communication skills and possesses the drive to deliver quality results on time in a dynamic, multi-disciplined, intensive and highly productive small team environment.

Responsibilities

1. Running Layout (FIRE) Extraction on client site to support onsite inspection application development.

2. Remote support Layout (FIRE) Extraction for the R&D and Demo Application development.

Qualifications

Bachelor's Degree or higher in electrical engineering. Degrees, such as statistics or IT-related discipline may work, depending on work experience.

Skill Set

o Core Technology & Knowledge

• Theoretical and practical experience in OPC/RET (Resolution Enhancement Technology)
• Comprehensive understanding of CMOS process flow
• Knowledge of mask fabrication and design rules (DRC)

o Software/Tool Proficiency

• Experience with OPC/Mask simulation tools:
• Mentor Graphics Calibre OPC/ILT
• Synopsys Sentaurus/Litho
• ASML Brion Tachyon
• Layout processing tools:
• Cadence, Synopsys, or KLayout
• Scripting & Programming:
• Hands-on experience with Linux
• Python, Perl, Tcl, Shell scripting
• Experience in large-scale data processing and automation

o Algorithm & Data Processing Skills

• Understanding of pattern matching, shape transformation, and data optimization
• Experience in OPC optimization using Machine Learning / AI (preferred)

o Analytical & Problem-Solving Skills

• Analysis and improvement of discrepancies between layout and actual pattern
• Experience analyzing SEM/E-beam inspection data
• Experience optimizing process window (PW) and depth of focus (DOF)

o Collaboration & Work Skills

• Experience collaborating with Design, Lithography, and Fab Process teams
• Experience modifying and optimizing designs based on customer/internal feedback
• Ability to read and understand English technical papers/datasheets and write reports

Pay Range

USD $120,000.00 - USD $160,000.00 /Yr.

Bachelor's Degree or higher in electrical engineering. Degrees, such as statistics or IT-related discipline may work, depending on work experience.

Skill Set

o Core Technology & Knowledge

• Theoretical and practical experience in OPC/RET (Resolution Enhancement Technology)
• Comprehensive understanding of CMOS process flow
• Knowledge of mask fabrication and design rules (DRC)

o Software/Tool Proficiency

• Experience with OPC/Mask simulation tools:
• Mentor Graphics Calibre OPC/ILT
• Synopsys Sentaurus/Litho
• ASML Brion Tachyon
• Layout processing tools:
• Cadence, Synopsys, or KLayout
• Scripting & Programming:
• Hands-on experience with Linux
• Python, Perl, Tcl, Shell scripting
• Experience in large-scale data processing and automation

o Algorithm & Data Processing Skills

• Understanding of pattern matching, shape transformation, and data optimization
• Experience in OPC optimization using Machine Learning / AI (preferred)

o Analytical & Problem-Solving Skills

• Analysis and improvement of discrepancies between layout and actual pattern
• Experience analyzing SEM/E-beam inspection data
• Experience optimizing process window (PW) and depth of focus (DOF)

o Collaboration & Work Skills

• Experience collaborating with Design, Lithography, and Fab Process teams
• Experience modifying and optimizing designs based on customer/internal feedback
• Ability to read and understand English technical papers/datasheets and write reports